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Altera_Forum
Honored Contributor I
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PLL on DE2-70

Hello I was wondering if there were any good simple examples for using the PLLs on the DE2-70 written in Verilog. I was also wondering what the max clk rate is that can be generated from the PLL's using the 50 MHz oscillator. If anyone knows of some good documentation on these things let me know, I would really appreciate it. Thanks!!!

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Altera_Forum
Honored Contributor I
24 Views

Apart from Cyclone II Hardware Handbook, the altpll megafunction userguide provides a complete documentation of PLL configuration options. I suggest to use the Quartus MegaWizard to create your Verilog code. The maximum clk rate mainly depends on the IO standard of the respective outputs, for internal clocks, about 400 MHz can be achieved, but I'm not aware of C II speed grade utilized with DE2-70. See the C II Hardware manula for details.

Altera_Forum
Honored Contributor I
24 Views

Hi Blue1440, 

 

The use of a PLL is very easy. You use the MegaWizard in Quartus to generate a module for the ALTPLL block. In its simplest configuration you only need an input clock inclk0 and one up to three output clocks c0, c1 and c2. In the MegaWizard you can specify your output clock frequency (by specifying the multiplication and division factors for your input clock frequency). 

 

More information on the ALTPLL module is given here (http://www.altera.com/literature/ug/ug_altpll.pdf).  

 

More information on PLLs in Cyclone-2 devices (such as on the DE2-70) is given here (http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf). 

 

 

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I was also wondering what the max clk rate is that can be generated from the PLL's using the 50 MHz oscillator. 

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With the Cyclone II: EP2C70F896C6 device you can use a maximum multiplication factor of your 50MHz DE2-70 input clock of 20 times. In theory this would result in a 1000 MHz clock. It will however be very difficult to make circuits work at this high speed. You will definitly only have very small circuits and need to use the TimeQuest timing analyzer. 

 

Hope this helps...
Altera_Forum
Honored Contributor I
24 Views

 

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In theory this would result in a 1000 MHz clock. It will however be very difficult to make circuits work at this high speed. You will definitly only have very small circuits and need to use the TimeQuest timing analyzer. 

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It's not difficult rather than simply impossible. Apart from maximum I/O and internal register toggle rates, Cylone II has a maximum PLL output frequency of 500 MHz (in fastest -6 speed grade). You're correct however regarding the relation of clock rate and design complexity. In the Cyclone II Hardware Handbook, maximum clock rates for typical design entities are listed, e.g. counters or FIR filters under timing specifications /performance.
Altera_Forum
Honored Contributor I
24 Views

I am a little confused. The mega function wizard asks for an input frequency for the PLL but I di not see it ask for an input pin or anything like that. I assume that I use a wire in the verilog to connect the input clk on the board to the pll then use the output of the PLL? Thanks fot the Help!

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