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Altera_Forum
Honored Contributor I
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Simple Verilog Question

Hello I am trying to make a simple multiplexer on the de2-70. I know there are many ways to do this but I was wondering why the following code does not do the task. 

Task: Read switch 17 if switch is 0 then switches 0 - 7 control leds 0 to 7 

if switch is 1 then switches 8 - 15 control leds 0 to 7 

 

I am using the given pinout to associate the pins to the labels in the code. 

The following code compiles but it acts funny. Only switch 8 in second switch bank 8-15 changes state of led0, while the rest of the switches do nothing no matter what value switch 17 is. Switches 7-0 only control leds 1-7 and do so no matter what position switch 17 is in. 

 

 

module Lab1 (iSW, oLEDR); 

input [17:0]iSW; 

output [7:0]oLEDR; 

assign oLEDR = (~iSW[17]&iSW[7:0])|(iSW[17]&iSW[15:8]); 

endmodule 

 

I know this is simple...but I am really just confused on the vector sintax. I would like to understand it better, so if anyone can fix the code or point me to a good tutorial on vector notation I would really appreciate it. 

 

THANKS!!!
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8 Replies
Altera_Forum
Honored Contributor I
73 Views

Altera_Forum
Honored Contributor I
73 Views

Hi Blue1440, 

 

 

 

--- Quote Start ---  

 

I know this is simple...but I am really just confused on the vector sintax. I would like to understand it better, so if anyone can fix the code or point me to a good tutorial on vector notation I would really appreciate it. 

 

--- Quote End ---  

 

 

In the Verilog code that you write, you use the Verilog "&" and "|" bitwise operators. They operate on corresponding bits in the vector(s) of the two operands, starting from the least significant bit.  

 

When you write: 

~iSW&iSW this means that the first vector is ~iSW[17] and the second vector is iSW[7:0]. When doing bitwise "&" it means that ~iSW[17] is ANDed ONLY with bit iSW[0]. So you should eather make a bit extension to your condition for switch 17 for example as: 

 

{~iSW,~iSW, ~iSW,~iSW,~iSW,~iSW,~iSW,~iSW}&iSW or better use the inline if-then-else "? :" construct as given below: 

 

module Lab1 (iSW, oLEDR); input iSW; output oLEDR; assign oLEDR = iSW ? iSW : iSW; endmodule  

Hope this helps!
Altera_Forum
Honored Contributor I
73 Views

sanmaro ist correct, this is a pitfall and sometimes hard to find but if you write it as suggested 

 

assign oLEDR = iSW[17] ? iSW[15:8] : iSW[7:0]; 

 

then is clear and easy to read and of course to check. 

 

but be aware of glitches as you only do combinatorical logic 

if possible better use a clock and registers for the output. 

declare oLEDR as a wire, add a register like 

reg [7:0] MyReg; 

always @ ( posedge MyClock ) 

MyReg <= iSW[17] ? iSW[15:8] : iSW[7:0]; 

 

and then assign the register to the output 

 

assign oLEDR = MyReg;
Altera_Forum
Honored Contributor I
73 Views

Thanks for the help 

 

Those examples worked very well. 

 

I assume you say using the clock to avoid glitches with the timing of the gates. I tried to write the code to use the 50MHz clk on the board for the clock to the mux so I wrote this code segment from the example you added.. 

 

module Lab1 (iCLK_50, iSW, oLEDR); 

input [17:0]iSW, iCLK_50; 

output [7:0]oLEDR; 

reg[7:0]LedReg; 

wire oLEDR; 

always @ (posedge iCLK_50) 

 

LedReg <= iSW[17] ? iSW[15:8] : iSW[7:0]; 

assign oLEDR = LedReg; 

endmodule 

 

but now I am getting the following error. 

 

Error: Can't place multiple pins assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[1] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[2] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[3] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[4] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[5] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[6] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[7] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[8] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[9] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[10] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[11] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[12] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[13] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[14] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[15] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[16] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[17] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[0] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

 

I had a simlar error with the switch number 7 on the DE2-70 board and fixed it from this post: 

http://www.alteraforum.com/forum/showthread.php?t=5851&gsa_pos=1&wt.oss_r=1&wt.oss=de2-70%20multiple... (http://www.alteraforum.com/forum/showthread.php?t=5851&gsa_pos=1&wt.oss_r=1&wt.oss=de2-70%20multiple...

 

but it is not working in this case. I was wondering if anyone sees what I did wrong. Thanks for the help!
Altera_Forum
Honored Contributor I
73 Views

 

--- Quote Start ---  

Thanks for the help 

 

Those examples worked very well. 

 

I assume you say using the clock to avoid glitches with the timing of the gates. I tried to write the code to use the 50MHz clk on the board for the clock to the mux so I wrote this code segment from the example you added.. 

 

module Lab1 (iCLK_50, iSW, oLEDR); 

input [17:0]iSW, iCLK_50; 

output [7:0]oLEDR; 

reg[7:0]LedReg; 

wire oLEDR; 

always @ (posedge iCLK_50) 

 

LedReg <= iSW[17] ? iSW[15:8] : iSW[7:0]; 

assign oLEDR = LedReg; 

endmodule 

 

but now I am getting the following error. 

 

Error: Can't place multiple pins assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[1] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[2] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[3] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[4] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[5] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[6] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[7] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[8] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[9] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[10] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[11] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[12] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[13] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[14] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[15] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[16] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[17] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

Info: Pin iCLK_50[0] is assigned to pin location Pin_AD15 (IOC_X49_Y0_N1) 

 

I had a simlar error with the switch number 7 on the DE2-70 board and fixed it from this post: 

http://www.alteraforum.com/forum/showthread.php?t=5851&gsa_pos=1&wt.oss_r=1&wt.oss=de2-70%20multiple... (http://www.alteraforum.com/forum/showthread.php?t=5851&gsa_pos=1&wt.oss_r=1&wt.oss=de2-70%20multiple...

 

but it is not working in this case. I was wondering if anyone sees what I did wrong. Thanks for the help! 

--- Quote End ---  

 

 

Hi, 

 

I have modified your source code. Look into the comments . 

 

module Lab1 (iCLK_50, iSW, oLEDR); 

input [17:0]iSW;  

input iCLK_50; 

output [7:0]oLEDR; 

reg[7:0]LedReg; 

wire [7:0] oLEDR; 

always @ (posedge iCLK_50) 

 

LedReg <= iSW[17] ? iSW[15:8] : iSW[7:0]; 

assign oLEDR = LedReg; 

endmodule 

 

// input [17:0]iSW, input iCLK_50; you specfied your clock input as 18-bit vector 

// wire oLEDR; you defined a single bit wire but assignment was a vector LedReg[7:0] 

// What about iSW[16] ? 

 

Kind regards 

 

Gerd
Altera_Forum
Honored Contributor I
73 Views

As pletz correctly wrote you did a mistake in defining your wires and the clock. 

these mistakes didn't have something to do with dual purpose pins you mentioned with your link. in fact the error message you have posted clearly states that your clock array can not place all array elements at that single pin of your device. 

 

with the code posted from pletz your module should work.
Altera_Forum
Honored Contributor I
73 Views

I agree to MSchmitt that you can add a clock to your design. This is because most of the designs are not purely combinatorial but sequential. 

 

As this is an educational toy example, there is no need for this example to use a clock. There is also no danger for glitches, races or hazards, as the functionality of this example is completley combinatorial. 

 

The example as a posted before in this thread is therefor OK and runs well without problems on the DE2-70.
Altera_Forum
Honored Contributor I
73 Views

Yep that code worked great. I was confused as to how those were supposed to be declared. Thanks again for the help!

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