Part V-Lab Exercise 1

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So after reading Part V like a few times,i fairly understand what does this examples wants me to do,and from the VHDL code given,i manage to get HEX0 going. 

 One problem is the statement of "you will need to use three instances of each of the subcircuits".What does this mean?Do i create 3 different VHDL codes and compiled to 1 like c++? or do i do everything in one page?  I am pretty confused with the code in bold given in the script.Could anyone explain to me what does it really mean? ------------------------------------------------------------------------  LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY chiong4 IS PORT (S,U,V,W : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6);  HEX1 : OUT STD_LOGIC_VECTOR(0 TO 6);  HEX2 : OUT STD_LOGIC_VECTOR(0 TO 6);  LEDR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));  END chiong4;  ARCHITECTURE Behavior OF chiong4 IS COMPONENT mux_2bit_3to1 PORT ( S, U, V, W : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); END COMPONENT; ------------------------------------------------------------------------------------------------- COMPONENT char_7seg PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  Display : OUT STD_LOGIC_VECTOR(0 TO 6)); END COMPONENT;  COMPONENT char_7seg1 PORT ( D : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  Display1 : OUT STD_LOGIC_VECTOR(0 TO 6)); END COMPONENT;  COMPONENT char_7seg2 PORT ( E : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  Display2 : OUT STD_LOGIC_VECTOR(0 TO 6)); END COMPONENT;  -------------------------------------------------------------------------------------------------- SIGNAL M : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN  LEDR<=S & W & V & U;  m0: mux_2bit_3to1  port map (s(1 downto 0),u(1 downto 0),v(1 downto 0),w(1 downto 0), m); h0: char_7seg  port map (m, hex0); h1: char_7seg1 port map (m, hex1); h2: char_7seg2 port map (m, hex2);  END Behavior; --------------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY mux_2bit_3to1 IS PORT ( S, U, V, W : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); END mux_2bit_3to1;  ARCHITECTURE Behavior OF mux_2bit_3to1 IS begin    M <= u when (s(0) ='0' and s(1) ='0') else   v when (s(0) ='1' and s(1) ='0') else  w when (s(0) ='0' and s(1) ='1') else  w;  END Behavior; --------------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY char_7seg IS PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  Display : OUT STD_LOGIC_VECTOR(0 TO 6));   END char_7seg;  ARCHITECTURE Behavior OF char_7seg IS begin    DISPLAY <="1000010" WHEN C = "00" ELSE  "0110000" WHEN C = "01" ELSE  "1001111" WHEN C = "10" ELSE  "1111111";    END Behavior;   LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY char_7seg1 IS PORT ( D : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  Display1 : OUT STD_LOGIC_VECTOR(0 TO 6));   END char_7seg1;  ARCHITECTURE Behavior OF char_7seg1 IS begin    DISPLAY1 <="1000010" WHEN D = "00" ELSE  "0110000" WHEN D = "01" ELSE  "1001111" WHEN D = "10" ELSE  "1111111";    END Behavior;   LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY char_7seg2 IS PORT ( E : IN STD_LOGIC_VECTOR(1 DOWNTO 0);  Display2 : OUT STD_LOGIC_VECTOR(0 TO 6));   END char_7seg2;  ARCHITECTURE Behavior OF char_7seg2 IS begin    DISPLAY2 <="1000010" WHEN E = "00" ELSE  "0110000" WHEN E = "01" ELSE  "1001111" WHEN E = "10" ELSE  "1111111";    END Behavior;

[Altera_Forum]

Question: 

1.Just to understand the instructions clearly,SW0-SW1 changes HEX0 and SW2-SW3 changes HEX1 and SW4-SW5 changes HEX2 right?From this code,it seems that whenever i change SW0 and SW1,HEX0-HEX2 changes?Why is this so?I cant figure out the 1st part of my problem here  2."Connect the switches SW9-SW8 to the select inputs of each of the three instances of the three bit wide 3 to 1 Multiplexers?Am i doing it right with the output M here?

[Altera_Forum]

Hello,  

Our lab instructions seem to be similar, with the only difference being that the bitwidths for our MUXes and the ammount of 7Segs we're using are different.   In the lab I am taking, I am told that I need to use boolean logic gates to do EVERYTHING tough. If i could use switches or if statements, I'd have been on to the next lab days ago!!! :D     --- Quote Start ---  One problem is the statement of "you will need to use three instances of each of the subcircuits".What does this mean?Do i create 3 different VHDL codes and compiled to 1 like c++? or do i do everything in one page?  I am pretty confused with the code in BOLD given in the script.Could anyone explain to me what does it really mean?  --- Quote End ---    No, you make instances of the modules that you've created in previous previous parts 3 and 4. The code in bold are actually representations of those instances. Look at my version of the top level design to see an example.  Now where I'm lost is, that I don't know how to make the MUXes scroll the text!! PLEASE HELP!! :confused:   top level - part 5  ARCHITECTURE Behavior OF Lab1_5 IS COMPONENT Lab1_3 PORT ( S, U, V, W, X, Y : IN STD_LOGIC_VECTOR(2 DOWNTO 0); M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END COMPONENT; COMPONENT Lab1_4 PORT ( C : IN STD_LOGIC_VECTOR(2 DOWNTO 0); Display : OUT STD_LOGIC_VECTOR(0 TO 6)); END COMPONENT; SIGNAL M0 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL M1 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL M2 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL M3 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL M4 : STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN Mux0: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(14 DOWNTO 12), SW(14 DOWNTO 12), SW(14 DOWNTO 12), SW(14 DOWNTO 12), SW(14 DOWNTO 12), M0); Mux1: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(11 DOWNTO 9), SW(11 DOWNTO 9), SW(11 DOWNTO 9), SW(11 DOWNTO 9), SW(11 DOWNTO 9), M1); Mux2: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(8 DOWNTO 6), SW(8 DOWNTO 6), SW(8 DOWNTO 6), SW(8 DOWNTO 6), SW(8 DOWNTO 6), M2); Mux3: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(5 DOWNTO 3), SW(5 DOWNTO 3), SW(5 DOWNTO 3), SW(5 DOWNTO 3), SW(5 DOWNTO 3), M3); Mux4: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(2 DOWNTO 0), SW(2 DOWNTO 0), SW(2 DOWNTO 0), SW(2 DOWNTO 0), SW(2 DOWNTO 0), M4); H0: Lab1_4 PORT MAP (M0, HEX0); H1: Lab1_4 PORT MAP (M1, HEX1); H2: Lab1_4 PORT MAP (M2, HEX2); H3: Lab1_4 PORT MAP (M3, HEX3); H4: Lab1_4 PORT MAP (M4, HEX4); END Behavior;  mux - lab 3 library ieee; use ieee.std_logic_1164.all; entity lab1_3 is port(S,U,V,W, X,Y : in std_logic_vector(2 downto 0); M : out std_logic_vector(2 downto 0) ); end lab1_3; architecture behavioral of lab1_3 is signal uvm, wxm, uvwxm : std_logic_vector(2 downto 0); begin uvm <= ((not (S(0) & S(0) & S(0))) and u) or ((S(0) & S(0) & S(0)) and v); wxm <= ((not (S(0) & S(0) & S(0))) and w) or ((S(0) & S(0) & S(0)) and x); uvwxm <= ((not (S(1) & S(1) & S(1))) and uvm) or ((S(1) & S(1) & S(1)) and wxm); M <= ((not (S(2) & S(2) & S(2))) and uvwxm) or ((S(2) & S(2) & S(2)) and y); end behavioral;  7segs - lab 4 library ieee; use ieee.std_logic_1164.all; entity lab1_4 is port(C : in std_logic_vector(2 downto 0); Display : out std_logic_vector(0 to 6) ); end lab1_4; architecture behavioral of lab1_4 is begin Display(0) <= ((not C(2)) and (not C(1)) and (not C(0))) or ((not C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (C(0))) or ((C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (C(1)) and (C(0))); Display(1) <= ((not C(2)) and (not C(1)) and (C(0))) or ((not C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (C(0))) or ((C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (C(1)) and (C(0))); Display(2) <= ((not C(2)) and (not C(1)) and (C(0))) or ((not C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (C(0))) or ((C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (C(1)) and (C(0))); Display(3) <= ((not C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (C(0))) or ((C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (C(1)) and (C(0))); Display(4) <= ((C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (C(0))) or ((C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (C(1)) and (C(0))); Display(5) <= ((C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (C(0))) or ((C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (C(1)) and (C(0))); Display(6) <= ((not C(2)) and (C(1)) and (not C(0))) or ((not C(2)) and (C(1)) and (C(0))) or ((C(2)) and (not C(1)) and (not C(0))) or ((C(2)) and (not C(1)) and (C(0))) or ((C(2)) and (C(1)) and (not C(0))) or ((C(2)) and (C(1)) and (C(0))); end behavioral;

[Altera_Forum]

Looks like changing my MUXes around was one way of solving the problem. You'll notice that the vector ranges of the MUX inputs all shift. Take a good look at this version and my last version posted. When changing the MUX selectors, nothing changes, cause all of them output the same thing in all situations, until the shifting was done. I knew i had to shift something, just wasn't sure where to do it. NOW I CAN GET SOME SLEEP XD. on to part VI tomorrow morning(well, later this morning). 

  Mux0: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(14 DOWNTO 12), SW(11 DOWNTO 9), SW(8 DOWNTO 6), SW(5 DOWNTO 3), SW(2 DOWNTO 0), M0); Mux1: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(11 DOWNTO 9), SW(8 DOWNTO 6), SW(5 DOWNTO 3), SW(2 DOWNTO 0), SW(14 DOWNTO 12), M1); Mux2: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(8 DOWNTO 6), SW(5 DOWNTO 3), SW(2 DOWNTO 0), SW(14 DOWNTO 12), SW(11 DOWNTO 9), M2); Mux3: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(5 DOWNTO 3), SW(2 DOWNTO 0), SW(14 DOWNTO 12), SW(11 DOWNTO 9), SW(8 DOWNTO 6), M3); Mux4: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(2 DOWNTO 0), SW(14 DOWNTO 12), SW(11 DOWNTO 9), SW(8 DOWNTO 6), SW(5 DOWNTO 3), M4);  -edit- sorry about the formatting, it does look better in the code editor.