Dear All,
I am trying to simulate the FFT IP core. I would like to ask for some advice on how to proceed and how to compare the output from the simulation with Matlab. Please find the procedure I have followed, the results, and the main logic from the testbench below.
- altera FFT IP core
- length: 8.
- input/output Order: Natural
- Data flow: Variable Streaming.
- Representation: Fixed Point.
- Data input width: 14 bit.
- Twiddle Width: 14 bit.
- Data output Width: 14 bit.
My testbench logic to test input data:
task fft_data;
integer i;
reg [13:0] test_data [0:7];
begin
data[0] = 14'd1;
data[1] = 14'd2;
data[2] = 14'd3;
data[3] = 14'd4;
data[4] = 14'd5;
data[5] = 14'd6;
data[6] = 14'd7;
data[7] = 14'd3;
for (i = 0; i < 8; i = i + 1) begin
@(posedge clk);
sink_real <= data[i];
sink_imag <= 14'd0;
sink_valid <= 1;
if (i == 0)
sink_sop <= 1;
else
sink_sop <= 0;
if (i == 7)
sink_eop <= 1;
else
sink_eop <= 0;
end
@(posedge clk);
sink_valid <= 0;
sink_sop <= 0;
sink_eop <= 0;
end
endtask
Matlab, after I created the FFT example design, I have the following results:
test data => x = [1, 2, 3, 4, 5, 6, 7, 3];
>> fft_ii_0_example_design_model
ans =
31.0000 + 0.0000i -8.0000 + 6.0000i -4.0000 - 1.0000i 0.0000 - 2.0000i 1.0000 + 0.0000i 0.0000 + 2.0000i -4.0000 + 1.0000i -8.0000 - 6.0000i
- What am I missing, and how should I proceed with simulation and debugging?
- Also, the calculation latency for the specific IP is 8, and the throughput latency is 16. Does that mean I should expect the source_real output after 16 cycles for each data input?
- Can you let me know if i can use for simulation the files on photo whaich are auto generated files from FFT IP core example design.
Thank you.
Link Copied
