Position-Counter VHDL in Quartus II question

Altera_Forum · ‎11-21-2011

Hi there, I'm new to this site and also new to using vhdl. I was wondering if I could have some help/suggestions for this question. Please and thank you!!:(

the question of my assignment:

1a)The counter has a 6 bit input. It counts up to 64 positions and then counts back down. Whenever the counter equals something, it stores a 12 bit input into a position. Write a VHDL for this part.

(This is what I did, but I'm not sure if I did it right >__< )

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

USE ieee.std_logic_arith.all;

ENTITY counterANDposition IS

PORT(

Clock, Reset, Up : IN STD_LOGIC;

Count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

Position : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)

);

END;

ARCHITECTURE behavioural OF counterANDposition IS

SIGNAL Count_Temp: STD_LOGIC_VECTOR(5 DOWNTO 0);

SIGNAL Position_Temp: STD_LOGIC_VECTOR(11 DOWNTO 0);

BEGIN

PROCESS(Clock, Reset)

BEGIN

IF(rising_edge(Clock)) THEN

IF(Reset='1') THEN

Count_Temp<="000000";

ELSE

Count_Temp<=Count_Temp+1;

END IF;

END PROCESS;

Count<=Count_Temp;

Position<=Position_Temp;

END;

Altera_Forum · ‎11-21-2011

I guess your counter is supposed to work this way:


PROCESS(Clock, Reset)
  BEGIN
      IF(rising_edge(Clock)) THEN
           IF(Reset='1') THEN
               Count_Temp<="000000";
           ELSIF (Up='1')
              Count_Temp<=Count_Temp+1;
           ELSE
               Count_Temp<=Count_Temp-1;
           END IF;
       END IF;
  END PROCESS;

Altera_Forum · ‎11-21-2011

I'm not sure I entirely understand the assignment...

--- Quote Start ---

The counter has a 6 bit input

--- Quote End ---

what is it doing with that input? For me the only inputs a counter can have is a clock, an enable signal, and a direction. You could use a 6-bit input to load a new value, but then you need to know on what condition you will load this value. Or did you mean a 6-bit output?

--- Quote Start ---

It counts up to 64 positions and then counts back down

--- Quote End ---

so it looks like a counter with automatic direction change.

--- Quote Start ---

Whenever the counter equals something, it stores a 12 bit input into a position

--- Quote End ---

Is that "something" a constant, or another output? What 12 bit input? What's a position?

Now about your code:USE ieee.std_logic_unsigned.all;don't use that. It's non standard and will create problems and confusion in the future as you learn more vhdl. Use the standard ieee.numeric_std.all library instead, and use the unsigned type for your counter value instead of std_logic_vector.

Your code only counts up and not down. You should create an additional "direction" signal to say if it counts up or down, and change that signal when you reach the extreme values.

As for the rest, it depends on what the assignment really means.