Intel® FPGA University Program
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CPU lab

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How can MV and MVI instructions be done in one cycle, supposed all events happen on clock edge? 


I am trying to draw a state diagram to illustrate how each instruction is carried out. My biggest problem is how things work. 


Upon startup, meaning everything is disabled. We want to turn on the Control Unit, this will take about one cycle to complete. Then next suppose the machine wants to read in Instruction, then we enable IR_in, which I supposed mean "enable IR to load in instruction from DIN line." 


Within that cycle, can we also read in the instruction from IR? Should we wait till the next cycle to read in the instruction? I ask this because we want to stop reading in instruction when an instruction is being executed... there is no memory in this simple CPU so we must reset all values on MUX to be "off" again at some pointer during the execution (so we know which register is write-enable for different instructions) 


Please guide me through this. Thanks.
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