Power Monitor is not working on Stratix 10

[alhussain779]

Hello,

I am trying to measure the power consumption of a design in my FPGA device using the Power Monitor utility that came with Board Test System. However, when I open it I get the following message:

""

Please check with the following methods:
-Ensure your computer is connected to the right board with USB cable.
-Type "jtagconfig --debug" in NIOS command shell, ensure both system MAX and FPGA are on JTAG chain.
-Restart this application.

""

And when I checked the log file of the bts program I found the following:

""

May 09, 2023 3:14:31 PM com.intel.bts.BtsView <init>
INFO: Board version: Rev D, chip version: HTPRD
May 09, 2023 3:14:31 PM com.intel.bts.ClientApp attachServer
INFO: [C:\intelFPGA_pro\19.1\quartus/sopc_builder/bin/system-console, --server]
May 09, 2023 3:14:31 PM com.intel.bts.ClientApp attachServer
INFO: Here is the standard output of the command:
May 09, 2023 3:14:37 PM com.intel.bts.ClientApp attachServer
INFO: TCP PORT: 59379
May 09, 2023 3:14:44 PM com.intel.bts.JtagInfo createDeviceInfoMapArray
INFO: 1 device detected: /devices/1SX280HH1(.|S3)|1SX280HH2|..@1#USB-1#DE10-Pro
May 09, 2023 3:14:44 PM com.intel.bts.ClientApp getMatchedBoardInfoArray
INFO: System Max matched: false, Fpga matched: true
May 09, 2023 3:15:13 PM com.intel.bts.BtsViewController buttonCloseOnAction
CONFIG: [Event -- Main window closing]

""

Note that the board I am using is from Terasic DE10-PRO SX

How can I solve the problem?

[AqidAyman_Intel]

Hello,

Thank you for reaching out to Intel FPGA Community.

It seems like a connectivity problem. This is my first guess.

Can you help to confirm if MSEL settings is correct and whether the devices involved and in the same JTAG path?

You can check using Intel Programmer also if the connection is detected or not.

If you have any other available board, can you confirm if there have the same issue?

[alhussain779]

Thanks for your reply,

the MSEL settings I am using is the Avalon-ST (x8) Mode (110) as shown in the picture below:

I also tried all the other modes with no luck.

I checked the jtag chain with command jtagconfig --debug and I got the following output:

""

1) DE10-Pro [USB-1]

     (JTAG Server Version 19.1.0 Build 240 03/26/2019 SJ Pro Edition)

     C322D0DD 1SX280HH1(.|S3)/1SX280HH2/.. (IR=10)

     Design hash 72AC4A992F0C88B023D5

     + Node 00486E00 Source/Probe #0

     + Node 00486E01 Source/Probe #1

     + Node 00486E02 Source/Probe #2

     + Node 00486E03 Source/Probe #3

     + Node 00486E04 Source/Probe #4

Captured DR after reset = (C322D0DD) [32]

Captured IR after reset = (001) [10]

Captured Bypass after reset = (0) [1]

Captured Bypass chain = (0) [1]

JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0

JTAG clock speed 24 MHz

""

Quartus Programmer shows only one device as shown in the following picture:

It seems like the MAX V CPLD is not in the JTAG path.

I have another board which is Arria 10 gx board and the power monitor works with it.

[AqidAyman_Intel]

Hi,

It seems system Max 10 is not detected in the JTAG chain causes the Power Monitor from the BTS can't be opened as there is mentioned in the message that you describe.

Also, from the log file, it also mentioned that the System Max 10 info array is not matched in the JTAG array.

Regards,

Aqid

[alhussain779]

Hi,

How can I make the JTAG detect the Max 10? Is there any guide that can help me in this?

I have searched over the Internet and did not find anything that could help.

Thanks

[AqidAyman_Intel]

Hi,

Can you share which version of Quartus software that you use? Can you first try to use the latest Quartus version if you are not using that?

Regards,

Aqid

[AqidAyman_Intel]

Hi,

Another solution that I can think of, you need to ensure that the version of JTAG related software like Jtagconfig or Jtagserver is matching with the version of Intel® Quartus® Prime software.

You can ensure the latest version of jtagserver is utilized by following the instructions in here:

https://www.intel.com/content/www/us/en/docs/programmable/683719/current/jtagconfig-version-setting-software.html

Regards,

Aqid

[AqidAyman_Intel]

Hi,

I wish to follow up with you.

Do need any more support on this? Do you have any updates?

Regards,

Aqid

[alhussain779]

Hi,

I would like to thank you for your help.

Regarding Quartus version I tried 18.0 , 19.1 and 20.3. All with no luck.

I checked that both Jtagconfig and Jtagserver matched Quartus 18.0 version. I did not check 19.1 and 20.3.

Now I will try the latest version of Quartus hoping it will fix the problem.

Regards,

Alhussain

[AqidAyman_Intel]

Hello Alhussain,

Thank you for your reply.

Let us know if you have any updates on that.

Regards,

Aqid

[AqidAyman_Intel]

Hello Alhussain,

Do you have any updates for this issue?

Regards,

Aqid

[alhussain779]

Hi Aqid,

I would to thank you for your concern.

I just tried the latest version of Quartus which is 23.1.

I used firstly NIOS II command  shell to test but it showed me the following message "jtagconfig: command not found"

So, I tried NIOS V command shell. jtagconfig command worked but still recognizing one device.

Do you have any other suggestions?

Regards,

Alhussain

[AqidAyman_Intel]

Hi Alhussain,

Thank you for your verification on the status with the latest version of Quartus.

I really regret that the issue is still there.

One thing you can check is the default setup for the board. Have you check the JTAG switch in the board where the switch is to enable MAX V in the JTAG chain?

Regards,

Aqid

[alhussain779]

Hi Aqid,

Yes, it's enabled.

I have also tried every possible JTAG switch configuration, no luck.

Regards,

Alhussain

[AqidAyman_Intel]

Snapshot from Intel® Stratix® 10 SX SoC Development Kit User Guide

[AqidAyman_Intel]

Snapshot from Terasic DE10-Pro SX User Manual

[AqidAyman_Intel]

Hi Alhussain,

I think this might be very likely with the Terasic board that you are using. I am not 100% confident on this but there might some differences between the board and our Intel Stratix 10 development kit.

When looking to Terasic DE10-Pro SX User Manual, I observed that the power monitor circuit is connected to S10 and not MAX 10 as our Intel® Stratix® 10 SX SoC Development Kit.

Refer to the attached snapshot from both documentations. We suspected Terasic have their own application written to read power monitor.

Regards,

Aqid