Problem with SDRAM controller and VGA controller in DE1

Altera_Forum · ‎10-31-2015

Hi all,

I want display image which stored in SDRAM through VGA in DE1. I use Qsys to do this and Control Panel to store image file bmp (already cut header) 640 x 480 in SDRAM

I already read many tutorial of Altera for Qsys but almost in DE2

When display in monitor, image is noise.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11347&stc=1

I try solve this problem but not success. This is code vhdl top Entity

--Implements a simple Nios II system for the DE1 board.--        CLOCK_50 is the system clock.
--        KEY0 is the active-low system reset.
--SDRAM ports correspond to the signals in Figure 2; their names are those
--used in the DE1 User Manual.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY vga_v1 IS
    PORT (
        KEY : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
        CLOCK_50 : IN STD_LOGIC;
        DRAM_CLK, DRAM_CKE : OUT STD_LOGIC;
        DRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
        DRAM_BA_0, DRAM_BA_1 : BUFFER STD_LOGIC;
        DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_WE_N : OUT STD_LOGIC;
        DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        DRAM_UDQM, DRAM_LDQM : BUFFER STD_LOGIC ;
        VGA_HS    : out std_logic;
        VGA_VS    : out std_logic;
        VGA_R     : out std_logic_vector (3 downto 0);
        VGA_G     : out std_logic_vector (3 downto 0);
        VGA_B     : out std_logic_vector (3 downto 0)
        );
END vga_v1;
ARCHITECTURE Structure OF vga_v1 IS
COMPONENT t_vga_v1 is
    port (
        clk_clk                : in    std_logic                     := '0';             --              clk.clk
        reset_reset_n          : in    std_logic                     := '0';             --            reset.reset_n
        sdram_controller_addr  : out   std_logic_vector(11 downto 0);                    -- sdram_controller.addr
        sdram_controller_ba    : out   std_logic_vector(1 downto 0);                     --                 .ba
        sdram_controller_cas_n : out   std_logic;                                        --                 .cas_n
        sdram_controller_cke   : out   std_logic;                                        --                 .cke
        sdram_controller_cs_n  : out   std_logic;                                        --                 .cs_n
        sdram_controller_dq    : inout std_logic_vector(15 downto 0) := (others => '0'); --                 .dq
        sdram_controller_dqm   : out   std_logic_vector(1 downto 0);                     --                 .dqm
        sdram_controller_ras_n : out   std_logic;                                        --                 .ras_n
        sdram_controller_we_n  : out   std_logic;                                        --                 .we_n
        vga_out_CLK            : out   std_logic;                                        --          vga_out.CLK
        vga_out_HS             : out   std_logic;                                        --                 .HS
        vga_out_VS             : out   std_logic;                                        --                 .VS
        vga_out_R              : out   std_logic_vector(3 downto 0);                     --                 .R
        vga_out_G              : out   std_logic_vector(3 downto 0);                     --                 .G
        vga_out_B              : out   std_logic_vector(3 downto 0);                     --                 .B
        sdram_clk_clk          : out   std_logic                                         --        sdram_clk.clk
    );
END COMPONENT;
SIGNAL DQM : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL BA : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
    DRAM_BA_0 <= BA(0);
    DRAM_BA_1 <= BA(1);
    DRAM_UDQM <= DQM(1);
    DRAM_LDQM <= DQM(0);
    --    Instantiate the Nios II system entity generated by the SOPC Builder.
    NiosII: t_vga_v1    PORT MAP (
        clk_clk => CLOCK_50,
        reset_reset_n => KEY(0),
        sdram_clk_clk             => DRAM_CLK,
        sdram_controller_addr     => DRAM_ADDR,
        sdram_controller_ba       => BA,
        sdram_controller_cas_n     => DRAM_CAS_N,
        sdram_controller_cke      => DRAM_CKE,
        sdram_controller_cs_n     => DRAM_CS_N,
        sdram_controller_dq       => DRAM_DQ,
        sdram_controller_dqm      => DQM,
        sdram_controller_ras_n     => DRAM_RAS_N,
        sdram_controller_we_n     => DRAM_WE_N ,
        
        vga_out_CLK         => open,
        vga_out_HS             => VGA_HS,
        vga_out_VS             => VGA_VS,
        vga_out_R              => VGA_R,
        vga_out_G              => VGA_G,
        vga_out_B              => VGA_B
        );
END Structure;

Qsys I used

http://www.alteraforum.com/forum/attachment.php?attachmentid=11348&stc=1

I think problem is timing SDRAM Controller in Qsys for SDRAM A2V64S40CTP Powerchip but i don't know how to config it.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11349&stc=1

Please help me, thank everyone

Altera_Forum · ‎11-01-2015

Implement a simple test pattern to start testing with. Even displaying a solid color screen correctly will help you eliminate problems with video timing. Once that is correct move on to displaying memory. I'd suggest doing standard memory tests with your SDRAM before you attempt to display an image. This will verify you have the memory controller working.

Altera_Forum · ‎11-02-2015

Thank answer Galfonz.

I found my problem is DRAM and SRAM. When I change Pixel Buffer to SRAM, screen is stable, haven't noise. Perhaps, because of Speed between VGA controller and SDRAM work.