Hi,I'm working on lab 8 of the university program, but my question is rather general. Using the mega wizard in quartus I've build a one port RAM. I've inserted the file to my design (in Active HDL), made the other exercises and compiled- everything went fine. I've then opened the Quartus and imported all the necessary files (making sure the top.vhd is at the top of the list, etc.) and started compilation. All went fine (success) except some weird critical warnings... All the inputs and outputs of the LPM file from the mega wizard have been added to the Pin Planner as if they were external I/O's (i.e., with Input or Output Terminal in Active HDL) and the Pin Planner have put them aside, issuing a warning that it cannot find the loaction of these pins. Well, these aren't pins! they are internal signals made by Quartus Mega Wizard! How and When have they become external pins? Can any one help me?:confused: Thx!
what is the "Top Level Entity" defined as in your project?Assignments->Settings->General? Is it your top module, or did it somehow get switched to the name of your ram instance. Pete