Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
1099 Discussions

SD Card IP Core : timing constraints questions

Altera_Forum
Honored Contributor II
807 Views

Hello, 

 

I'm using the Altera SD Card IP Core with Nios II, and I have a few questions regarding the timing constraints. 

 

The Doc says :  

--- Quote Start ---  

Finally, it is important to 

set Tco and Tsu constraints for the SD card ports. Both parameters should be set to not more than 10ns. Should the 

parameters be omitted during design compilation, it is possible that the core may malfunction. 

--- Quote End ---  

 

 

But should I affect constraints to the 4 sd card output ports (including the clk one)? 

 

And what will be my reference clock for that, the clk input pin (50Mhz) or as I have seen on some thread, the sd card clock output port? 

 

Thanks a lot for the help!
0 Kudos
0 Replies
Reply