Stratix10 FPGA PAM4 signal

[Lily1234]

Hi all,

I am doing some research of PAM4 receiver. From the file of doucment of Stratix10  E-tlie transceiver PHY  user guide, I still have one question want to confirm, could you please give me some suggesstion?

For the PAM4 signal,  I/O standard is  LVPECL, I am very confused, LVPECL is used for coms, that means after LVPECL, the output is 0 or 1. If it is possible ro send a 20G analog PAM4 signal to this FPGA?

Below is the the stratix 10 doucment I used. Please see the page67, present the E-TILE receiver specifications.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf 

Thank you so much!

Lily

[CheePin_C_Intel · Accepted solution]

Hi Lily,

As I understand it, you have some inquiries related to the S10 E-Tile trasnceiver. For your information, the S10 E-Tile Receiver support data rate up to 57.8Gbps for PAM4 mode. The LVPECL is the IO standard selected but as for the receiver specs, you should refer to the E-Tile datasheet.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[Lily1234]

Hi Chee,

Sorry for the late response, I really appreciate your kindly reply. But i still feel confused about how to process PAM4 signal. 

For the I/O standard LVPECL, it used to receive PAM4. Does it have any demand for PAM4 EYE(like noise, three eye width and eye height)?

If there are have any document about PMA4 test result in the FPGA? I think it will be very useful to us to understand the question.

Thanks again ! Looking forward for you reply.

Best regards,

Lily