Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
1049 Discussions

Support to resolve warnings on Quartus 2 for Cyclone 4 E device

Altera_Forum
Honored Contributor I
779 Views

Hi, 

 

I am running altera's LCD design on Quartus 2 for Cyclone 4 E device and getting below warnings.Could you please assist to solve these. 

 

 

1) "pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. 

 

 

As per AN447 I did below pin configuration but still getting same warning.CLOCK_50 Location PIN_Y2 Yes 

 

CLOCK_50 I/O Standard 3.3-V LVTTL Yes 

 

CLOCK_50 PCI I/O On Yes 

 

 

 

I am not sure whether should I explicit do the assignments for PCI I/O as shown above but in AN 447 its mentioned that "The Quartus II software enables the PCI-clamp diode on the assigned input, bidirectional, or tristated output pins by default using the 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards" 

 

 

2)Warning (332060): Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment. 

Warning (332061): Virtual clock CLOCK_50 is never referenced in any input or output delay assignment. 

I have generated .sdc file having one constraint "create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 }" 

 

 

 

3) One more Query I am running altera's LCD design in which GPIO pins are assigned as shown below,even when they are not being used in design. My question is why they driven Z even they are not used in design.  

// All inout port turn to tri-state 

assign GPIO = 36'hzzzzzzzzz 

 

 

 

Thanks, 

Gagan 

0 Kudos
0 Replies
Reply