Intel® FPGA University Program
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Instantiating Audio IP Core correctly with DE2 board

Altera_Forum
Honored Contributor II
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Hello, 

 

I try to do my own synthetizer using Qsys, VHDL and Eclipse Nios II (c program). 

 

My first step was to test the sound output. I start by ready datasheet about the Audio IP Core of the University Program. They recommand to instantiate the audio and video config core with the Audio Core. Also, to use the external clocks for de board peripherals core to choose the proper clock settings for the Audio Core (wich is the Wolfson WM8731 Codec and use a 12Mhz clock for data sampling). I did all that and make a double check for all setting. My Qsys system can be generate properly and my VHDL can be compile too. But when a program my DE2 board with the .sof all I have on the Line Out output is very loud noise

 

I attach my VHDL file so you guy can check my top-level. I really don't know what I do wrong. 

 

Help will be appreciate! 

Thanks
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