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Altera_Forum
Honored Contributor I
713 Views

UP2 Development Kit, Sync Problem?

Hello! 

 

I am trying to implement stream cipher on UP2 Dev Kit and provide communication between this board and PC using USB. To do that I decided to use FT245BM. 

 

So I wrote the controller that is responsible for reading bytes from FTDI, encrypting them using stream cipher and sending them back to the PC. It's working almost fine. 

 

The problem is... There is something strange that happens quite ranndomly. 

 

For debugging purposes I am sending zeros to encrypt. Since the encryption uses XOR operation, the encrypted data is just keystream generated by cipher. 

 

So let's say that I send 3 bytes (zeros) to encrypt. The keystream that should be generated looks like this: 

0x7B, 0x97, 0x8C 

 

The keystream that is sent back to PC looks like this: 

0x7B, 0x97, 0x19 

 

So when you look closer at third byte you will notice that: 

 

0x8c = 1 0001100 

0x19 = 0001100 1 

 

The first bit from 0x8C just disappears! The most right bit from 0x19 is just the next generated bit (correct one). As i said this happens randomly. It's not that it's always 3th byte. It could be 5th, 10th, 100th byte. Sometimes it doesn't even occur. 

 

I've checked source code, and everything looks as it should. All outputs are sync with clock. State Machine generated by RTL Viewer looks ok. 

 

Any advice? This is extra important to me, so any advice will be very appreciated!
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Altera_Forum
Honored Contributor I
21 Views

hi, i have a similar problem could you post your code for ft245

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