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Critical Warning: Timing requirements not met and SRAM problems

Altera_Forum
Honored Contributor II
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Hello 

 

I had a design that works properly on a DE2 board. I am trying to implement the same design on a DE2-115 board, and I found some troubles. 

 

The design seems to work well until I try to use the NIOS II with the external SRAM memory. When I try to debug the software (and, a simple "Hello world", too), memory validation fail. 

 

I modify just a bit the vhdl code and recompile and it seems to work....  

I modify just a bit the vhdl code and recompile and it doesn't work.... 

 

Finally I find the following warning: 

"Critical Warning: Timing requirements not met" 

 

Could it be the cause of my trouble? How can I fix it? 

 

Sorry for my poor english sintaxis. 

Thanks.
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Altera_Forum
Honored Contributor II
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Well, put simply, "Timing requirements were not met" and thus your design will, probably, not work. 

 

You need to track down the failing paths and see why they're failing.
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Altera_Forum
Honored Contributor II
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search for the timequest tutorial at www.alterawiki.com

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