I need assistance on implementing the USB interface on the Cyclone V GT FPGA Development Kit. I understand that the board has a Cypress CY7C68013A connected to the FPGA through a MAX II CPLD. By default the USB functions as an embedded USB Byte Blaster II, but can be disabled when an external USB Byte Blaster is connected to the JTAG connector. I assume that when the embedded USB Byte Blaster II is disabled, I can the configure it to interface directly to the FPGA so that I stream data. From the schematics, it looks like the lines are connected from the Cypress chip to the FPGA via a MAX II CPLD. I don’t have detailed information on how the MAX II function when the embedded USB Byte Blaster II is disabled. However, when I use Cypress utility (Cypress Control Center), it could not find the Cypress chip, so I am not able to programmed it. From Window device manager, it still recognize the USB as an Altera Byte Blaster even though it has been disabled by the connected external USB Byte Blaster.
I would appreciate it if someone has solution or example I can use.
Thank you for contacting Intel community.
Kindly refer to Cyclone V GT development kit userguide and USB Blaster userguide:
Let me know if you need further information.
I have already gone through the relevant documentation and I cannot find any information regarding my specific problem. I cannot find any information regarding implementing a USB to FPGA interface on the development board, which seems to be feasible from the schematics.
I am sorry to let you know that we do not provide the schematic design for free. You will need a paid license to get the schematic.
Apologize for the incoviniences.
Sorry for the misunderstanding.
This might happen when you are using Cypress utility (Cypress Control Center) as this is 3rd party device.
I would like to suggest to use Quartus Programmer to run the project.