Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises

University program vwf

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i have 3 verilog files and three vwf file correspond to the verilog file 

ex: first.v, second.v, third.v, first.vwf, second.vwf, third.vwf 


i know that if i want to run simulation on one of the vwf file, i have to set it to top entity. 

ex: if i want to run simulation on third.vwf, i need to set third to top entity.  


The first and second vwf window that showed up was correct but when i try to run the third, it showed up the second vwf window even though i already set third to top entity. 


Can i know where is the problem and how do i fix it so that come up with correct window.  

p/s:third is the module that combine first and second
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