Why are the propagation delays simulated by my Quartus software clearly wrong?

[DWels3]

I've designed a circuit of 39 two-input AND gates. The output of the previous feeds into one of the input of the next, and the second input has a logic '1' always at the input. I then use a waveform file to simulate what happens when the first and gate has one of the inputs go from low to high. This should send a cascading rise along the chain until I see the outcome appear at the very last gate. Also along the way I have output pins to monitor the signal as it runs through the chain. See the photo attached.

My question is why does the simulation show the final output going high BEFORE some of the outputs in the chain have gone high? Clearly something has gone very wrong!

Simulated mode set to 'Timing' in the Simulator Settings window but I don't know what else is wrong. I would really appreciate any insight as to what settings I have put wrong.

Many thanks all 🙂

[KhaiChein_Y_Intel]

Hi,

May I know the software edition, software version and device you are using?

Thanks

[DWels_3]

Hi,

I’m using Quartus II 8.1 Web Edition, build version 163. Also the HDL is implemented on a Cyclone EP1C20F400C7.

Thanks

[KhaiChein_Y_Intel]

Hi DWels 3,

Referring to https://www.intel.com/content/www/us/en/programmable/documentation/gtt1529956823942.html

Gate level timing is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families.

Thanks.

[GuaBin_N_Intel]

How did you select those signal gd[x] in the simulation? Are all of gd[X] are connected to IO port? Can upload tech map viewer for that implementation?