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Altera_Forum
Honored Contributor I
811 Views

Writing to SRAM from VHDL and using NIOS

Dear All, 

 

For a schoolproject I am working on a spectrum analyzer. I have downloaded the Altera University program and I modified de C code so it will display a nice coordinate system. Outside NIOS I programmed a FFT in VHDL with input from an external ADC. So far this all works. 

 

What I want to do now is build a bar graph. I would like to write this directly to the SRAM from VHDL but this is already occupied by NIOS. So I understand I now need to make a custom peripheral to acces this SRAM from VHDL but I can't figure out how. I do understand VHDL but all things that have to do with NIOS and SOPC are completely strange to me. 

 

Please give me some tips.
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11 Replies
Altera_Forum
Honored Contributor I
54 Views

What you basically need is to create a component with an Avalon Memory Mapped Master interface. Then in SOPC builder connect that master interface to the SRAM, and it will automatically be shared between the Nios CPU and the memory. 

You will find more detail about the avalon interfaces in this document: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
Altera_Forum
Honored Contributor I
54 Views

Does this custom component also needs to be connected to the NIOS data master?

Altera_Forum
Honored Contributor I
54 Views

No, you always connect a master to a slave. If two masters (such as the NIOS CPU and your own component) are connected to the same slave, it will then be shared.

Altera_Forum
Honored Contributor I
54 Views

Ok, so I found this: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html. I now added it in SOPC and gave it the requirements I think it should have. Only thing that is not clear to me now is how I reach this entity from hardwarelevel.

Altera_Forum
Honored Contributor I
54 Views

I'd offer better to use DMA, since You'll know what region of memory is used by Your needs and what region of memory is used by Nios. Since You probably have streaming interface with no backpressure, then I'd offer to use SGDMA.

Altera_Forum
Honored Contributor I
54 Views

It would help me very much if someone explained me the steps that have to be taken to make a solution. I am busy for days now but the more I know, the more I get confused. 

 

The goal here is that I want to give in a 32bit SRAM adress with the 16bit value, just like it can be done from C. But now from a VHDL perspective. I know, I am a complete FPGA noob:D, but I need to get the job done. I would appreciate it very much if someone could give me a bit of guidance.
Altera_Forum
Honored Contributor I
54 Views

A DMA can be a good solution if you have a big stream of data to transfer to or from memory. In that case you could use the Scatter-Gather DMA component from Altera (you'll find it in SOPC builder) in a stream-to-memory or a memory-to-stream configuration, and in your custom component just provide an Avalon Stream interface. 

If you just need to write a value to an address this may be overkill though, and it could be better to write a component with an Avalon Memory Mapped Master interface. In that case the write transaction is rather simple, just put the address and data value to the correct vectors, assert the write signal and wait for the wait_request signal to be deasserted. You should find timing diagrams in the specification. 

In most cases you will need a way to configure your component from the software (at least to say which address to use) so you will also need an Avalon Memory Mapped Slave interface to provide configuration registers. If you have a look at the chapter 10 of the sopc user manual (http://www.altera.com/literature/ug/ug_sopc_builder.pdf) you should find an example of such a setup.
Altera_Forum
Honored Contributor I
54 Views

Thank you for your information Daixiwen! I will read the SOPC User Manual before doing anything :) A future problem I see is that I don't know what input vectors and signals the Altera University SRAM has exactly.

Altera_Forum
Honored Contributor I
54 Views

Alright, so i'm using the MM templates from altera now. I added the write master to SOPC and linked the Master to the SRAM. Now I want to control the "conduits" from a VHDL entity. What I see is this: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=6634  

 

Can I just make a VHDL file and port map to this master_template_0 component or do I have to use the write_master component?
Altera_Forum
Honored Contributor I
54 Views

I figured it out:) I now got it portmapped in my toplevel. Now trying the system, but i can't see things changing on my screen. 

 

Do you guys think I could use the write template from Altera directly to the SRAM controller from the University program or do I have to modify it in some way? 

 

Thanks in advance!
Altera_Forum
Honored Contributor I
54 Views

How did you connect your component to the SRAM controller? If you do it in SOPC builder, you don't really have to care about the SRAM controller, or what kind of memory you are using. That's the big advantage of using Avalon memory mapped interfaces, your design can work with any kind of memory, as long as it is supported by SOPC builder. 

Are you using SignalTap? You can use it to monitor your component and see what it is doing.
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