Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,020 Views

converting RAW to RGB

Hi there. I am a very new beginner to fpga design. I am using a DE2-70 board with a camera and LCD kit. 

 

Right now, i have attached a picture of what a demo program essentially does. My job is to find out what is going on during the RAW2RGB process.  

 

I have attached the source code and i was wondering if someone could describe to me what is going on? I am totally in the dark. 

 

For instance, what does this bit of code do: 

 

always@(posedge iCLK or negedge iRST_n) 

begin 

if (!iRST_n) 

begin 

rRed<=0; 

rGreen<=0; 

rBlue<=0;  

end 

 

i know that it sets rRed,rGrean,rBlue to zero, but i have no idea what function it produces, and what kind of condition that would be! 

 

Also what do the variables X_cont and Y_cont mean? 

 

Someone please help! 

Thanks! 

Allen
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
64 Views

Without going in to your code in detail I can offer the following advice. 

 

http://www.asic-world.com/verilog/ 

 

Contains a lot of info on Verilog coding which may be of interest. 

 

The code fragment you posted is a bit out of context, the code following is important to. 

 

always@(posedge iCLK or negedge iRST_n) 

begin 

if (!iRST_n) 

begin 

rRed<=0; 

rGreen<=0; 

rBlue<=0;  

end 

 

else if ({mirror_sw,iY_Cont[0],iX_Cont[0]} == 3'b011) 

begin 

if (iY_Cont == 12'd1) 

begin 

rRed<=wData1_d1; 

 

 

Basically this means that the code following the always is executed on a rising edge of iClk (This is the clock) or a falling edge of iRst_n (This is a reset). 

 

The first if(iRST_n) is executed when when iRST_n = 0; 

 

The else part is executed when iClk is rising. This is the synchronous part of the process and controls the inputs to flip flops. 

 

These are just a few pointers and I really suggest that you read a good tutorial on Verilog programming. 

 

Good luck
Altera_Forum
Honored Contributor I
64 Views

oh yeah i know how to read verilog, sorry if i didnt make it clear. but my problem is how what the concept is in behind converting raw data into rgb data using verilog. Like for instance if the code goes through alignment of rgb data.  

Thanks!
Altera_Forum
Honored Contributor I
64 Views

raw is apparently related to the data frame of the camera module. You should consult the respective datasheet, to understand what is converted to RGB video here. 

 

To my opinion, the informative substance of Terasic demonstration code is mostly converging to zero, also in this case.
Altera_Forum
Honored Contributor I
64 Views

thanks for the help :) 

does anyone know what line_buffer is for?  

 

Line_Buffer L1 ( 

.clken(iDval), 

.clock(iCLK), 

.shiftin(iData), 

.shiftout(), 

.taps2x(wData0), 

.taps1x(wData1), 

.taps0x(wData2), 

);
Altera_Forum
Honored Contributor I
64 Views

A linebuf should be expected to buffer a video scan line. You can clarify this by checking the parameters used with the respective tap megafunction.

Reply