hello im new to the whole fpga programming scenario and im trying to implemnent a niosII processor on a cycloneII FPGA(on a DE2 board).in addition to my niosII processor i require some sort of additional circuitry to divide my 50Mhz clock signal to 100Hz. I was trying to do this using the LPM_COUNTER megafunction. I was able to create an up counter with a 26bit output but my problem is to get a single output of that to my processor. Im using the block diagram editor. My counter output is a 26bit bus so i cant just take the 24th pin and connect it to an input in my processor. I just want to get a single input to my processor after 500000 counts. How can i achive this with the LPM_COUNTER? or any other circuit? (besides building the whole divider using logic) please help :(
PLL will work for sure if you dnt want to peep into count stuffs,but if you want to use LPM_COUNT then i think it wont workActually I feel that if you want to connect with counter policy then use logic,it will be more easy than using mega function reason: Suppose you take 5 bit count (0 to 31),and for the required output clock,you need to stop your count at 30,then using megafunction,how will you achieve this?because if your count is 5 bit then it will be reset only after 31 only not in between (in case of up counter) But using your own logic,you can provide condition to stop after some count to get exact frequency. After that you can create block symbol from that hdl file. i have attached one verilog file and test bench based on your question,i think it will work for 50 mhz input and 100 hz output
Hope this will help you.
thanks a lot.. can you please direct me to some place where i can learn about PLLs? for this laboratory we are only supposed to use the block diagram editor.. thats why i was looking for some component under megafunctions.. im not sure how to incorporate written verilog code into the block diagram editor.. because inorder to connect the divider to the processor i have to use the block diagram editor
--- Quote Start --- Please PLL, not LPM_COUNTER --- Quote End --- @waiyung Have u generated 100 Hz from 50 Mhz on DE2 by PLL? PLL input and output frequency min and maximum frequency ranges depend on the FPGA that u select and multiplication/division factor that specs says about it. So i dont know if PLL can generate 100 Hz from 50 MHz for DE2 board. @normad To know better PLL,best possible thing is to read PLL IP core guide from avalon documents. Even if you will not able to understand at once,it will help you a lot.
thanks i think im gonna do it using logic.. pll seems too advanced for me.. im really sorry for the trouble but could you be kind enough to tell me how to generate the block symbol from the verilog file?
First of all "Don't say sorry"Now i think you dont need think about the verilog file because i have provided and it will work so dont worry In left pane of quartus project navigator window,click on "files" tab and right click on your required verilog file ( for eg.it is f_divider.v),you will see "create symbol files for the current file".click on that. Now you made block symbol from your verilog file. Hope this will help you little and don't say sorry again.No body is perfect :)
Nios II processor will not function at 100 Hz. There is a minimum clock frequency requirement on Nios II processor, it is in the MHz range. I cannot recall the exact frequency value though.