error budget model for the measurement system with MAX 10 FPGA Device

[bruceylee]

hello,  intel tech support: 

i will appreciate if you share with me an example of error budget ( such as output voltage) due to 

1) Gain Error due to Resistance Tolerance 

2) Internal Offset Voltage (Vios) Error 

3) Input Current Error 

4) CMRR Error 

5) PSRR Error 

an example of error budget analysis is enclosed for reference. 

thanks

jason 

[NurAiman_M_Intel]

Hi,

Thank you for contacting Intel community.

Apologize for the delay in response. This is to update that we are still pending the answer from our internal team. We will get back to you once we have the findings.

Thank you for your understanding.

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Per my checking, we follow JEDEC guidelines on process technology and reliability qualification methods.

All our process and product development efforts, including performance and reliability evaluations, have some form of error budgets. However, we don’t share this information as only the final product matters to customer. The final product conforms to JEDEC guidelines.

Hope this clarify.

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you