hello, can anybody tell me how to use alt_up_video_dma_draw function in quartus 2018

[Deshi_Intel]

hi, You can find out more info on the Intel FPGA university program IP in below link https://www.intel.com/content/www/us/en/programmable/support/training/university/materials-ip-cores.html For your case, i believe you can checkout the video IP suite pdf doc in the above link. thanks. regards, dlim

[rkaib]

thanks dlim for your tip, but can you be more specific as I did not find in which ip core i can find how to use alt_video_dma_draw function as it is a bit different in quartus 18.1 version. To be more precise I am reading an .hex image initialised in an on chip memory in nios2, but the data I am getting is different from the data contained in the .hex file. I am investigating this function that draw pixels in vga screen which is not displaying the right image.

I am quit happy to provide you with more details about the quartus project i am using if you need them. thanks

[Deshi_Intel]

HI, I am referring to the "video IP suite" doc in the university program link. You are right. I can't find alt_video_dma_draw IP in the doc nor Quartus v18.1 standard edition as well. Are you using very old Quartus version that either the IP has obsolete or changed name to something else ? If you can refer to the right IP name for guideline from the user guide doc then perhaps you can find some clue on how to debug your issue. Alternatively you can also try google for some similar example or reference design to help cross check with you design Thanks. Regards, dlim

[rkaib]

Hi dlim,thanks for your last reply,

I am using Quartus v18.1, in fact I can use other functions an data are correctly displayed on the screen (like alt_up_pixel_buffer_dma_clear_screen(), and alt_up_pixel_buffer_dma_draw_hline() ).

my problem is that thae data I am reading from the onchip memory are not the actual data, am I missing something ? (like addressing configuration or something).

the .hex file is attached to have an idea (which is an image).

I can provide other information if needed. thanks

[Deshi_Intel]

Hi, I am assuming your design configured all the IP setting correctly and there is no design timing closure concern else this is the first step that you need to check. - For instance, if you drill further into VGA_Subsystem then it should show you the exact IP name that can match back with "video IP suite" doc For the onchip memory issue debug - Have you managed to isolate the issue is with memory write issue, memory read issue or memory content corruption issue or VGA display IP issue ? For memory write/read issue : - Memory write/read issue could be due to address mapping issue or design timing closure issue For memory content corrupted issue : - How do you generate the onchip memory hex file content ? - Do you have other hex file content that you can load into to compare video output result ? For VGA display IP issue : - You want to checkout video IP suite doc to ensure you configure all the setting correctly that match with your hardware board - You can also keep your design simple for debug to slowly disable IP feature in VGA subsystem to find out where is the culprit. Thanks. Regards, dlim

[rkaib]

thank you dlim,

thanks for all this effort,

I will double check these points one by one and keep you updated as soon

as I can, regards

[Deshi_Intel]

sure. Good luck in debugging !