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.sof file not being created

Altera_Forum
Honored Contributor II
818 Views

Hi, 

 

After simulating my verilog file, .sof file is not being generated by default in order for me to program my file to the de1 board. I'm unsure why it's not producing these files.
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3 Replies
Altera_Forum
Honored Contributor II
100 Views

 

--- Quote Start ---  

Hi, 

 

After simulating my verilog file, .sof file is not being generated by default in order for me to program my file to the de1 board. I'm unsure why it's not producing these files. 

--- Quote End ---  

 

 

Maybe you don´t have a license file.
Altera_Forum
Honored Contributor II
100 Views

Look in the compilation report and search for "license". See what you find. Also, see if you are getting a "<design_name>_time_limited.sof" file. 

 

Jake
Altera_Forum
Honored Contributor II
100 Views

You can download a web edition of QII.

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