Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
1147 Discussions

.sof file not being created

Altera_Forum
Honored Contributor II
‎12-22-2009 08:26 AM
927 Views

Hi, 

 

After simulating my verilog file, .sof file is not being generated by default in order for me to program my file to the de1 board. I'm unsure why it's not producing these files.
0 Kudos

Link Copied

3 Replies
Altera_Forum
Honored Contributor II
‎12-22-2009 02:39 PM
209 Views

 

--- Quote Start ---  

Hi, 

 

After simulating my verilog file, .sof file is not being generated by default in order for me to program my file to the de1 board. I'm unsure why it's not producing these files. 

--- Quote End ---  

 

 

Maybe you don´t have a license file.
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎12-22-2009 08:18 PM
209 Views

Look in the compilation report and search for "license". See what you find. Also, see if you are getting a "<design_name>_time_limited.sof" file. 

 

Jake
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎02-12-2010 04:23 PM
209 Views

You can download a web edition of QII.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.