Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
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.sof file not being created

Altera_Forum
Honored Contributor II
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Hi, 

 

After simulating my verilog file, .sof file is not being generated by default in order for me to program my file to the de1 board. I'm unsure why it's not producing these files.
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi, 

 

After simulating my verilog file, .sof file is not being generated by default in order for me to program my file to the de1 board. I'm unsure why it's not producing these files. 

--- Quote End ---  

 

 

Maybe you don´t have a license file.
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Altera_Forum
Honored Contributor II
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Look in the compilation report and search for "license". See what you find. Also, see if you are getting a "<design_name>_time_limited.sof" file. 

 

Jake
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Altera_Forum
Honored Contributor II
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You can download a web edition of QII.

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