I am trying to integrate SDRAM controller into my project. I am using Modelsim for simulations and Precision for synthesis. I could not write the whole controller code, so thought to integrate sdram_0.v into my design. But I am facing issues. My test component is continuously asserting rd with address on sdram controller, but I am just reading the 0th location, which I suppose is just available at the SDRAM output. Is there any other proper sequence to do so? I suppose PLL is not needed in my design as I am just intending to read 1 location at a time and am using 50MHz clock. Looking forward for a quick reply! Regards.