Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
1081 Discussions

vhdl stopwatch with LPM RAM

Altera_Forum
Honored Contributor II
733 Views

Hi,  

I am doing a lab assignment about a VHDL stopwatch. 

this watch can store 16 32-bits timestamp in the memory. 

and when readmode = '1', the stopwatch will show the timestamps. 

 

below is my code.(the other modules are working fine, only this one doesn't work yet.) could anybody tell me what is wrong with it? 

I really appreciate it. 

 

 

--- Quote Start ---  

 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

use ieee.std_logic_unsigned.all; 

use ieee.numeric_std.all; 

entity stopwatch is 

port 

clk : in std_logic; 

readmode : in std_logic; 

reset : in std_logic; 

store : in std_logic; 

data_ram : in std_logic_vector(31 downto 0); 

data_clock : in std_logic_vector(31 downto 0); 

addr_user : in std_logic_vector(3 downto 0); 

ram_write_en: out std_logic; 

addr : out std_logic_vector(3 downto 0); 

data : out std_logic_vector(31 downto 0) 

); 

end stopwatch; 

ARCHITECTURE arch_stopwatch of stopwatch is 

TYPE state_type IS (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16); 

signal state : state_type := s0; 

signal stage : std_logic_vector(3 downto 0); 

signal flag : std_logic_vector(1 downto 0); 

signal c_store, n_store : std_logic; 

signal fall_edge : std_logic; 

 

begin 

flag <= reset & readmode; 

n_store <= store; 

fall_edge <= c_store and ( not n_store ); 

 

process(clk, reset) 

begin 

if( reset = '1' ) then 

c_store <= '1'; 

elsif( rising_edge(clk) ) then 

c_store <= n_store; 

end if; 

end process; 

process  

variable r_counter : std_logic_vector(3 downto 0); 

begin 

WAIT UNTIL (clk'event and clk = '1'); 

if( flag = "10" or flag = "11" ) then 

stage <= "0000"; 

state <= s0; 

ram_write_en <= '1'; 

--addr <= (others => '0'); 

data <= (others => '0');  

------------------------reset Memory------------------------ 

for i in 0 to 15 loop 

addr <= r_counter; 

r_counter := r_counter + 1; 

end loop; 

------------------------------------------------ 

 

elsif( flag = "00" ) then  

data <= data_clock; 

-------------store time--------- 

CASE state IS 

WHEN s0 =>  

ram_write_en <= '0'; 

stage <= "0000"; 

state <= s1;  

when s1 => 

if(fall_edge = '1') then 

addr <= stage; 

ram_write_en <= '1'; 

stage <= stage + 1; 

else 

ram_write_en <= '0'; 

end if; 

 

if( stage = "1111" ) then 

state <= s2; 

else 

state <= s1; 

end if;  

when s2 => 

when others => 

state <= s0;  

END CASE; 

---------------------------------  

elsif( flag = "01" ) then 

ram_write_en <= '0'; 

addr <= addr_user; 

data <= data_ram; 

end if; 

end process;  

end arch_stopwatch; 

 

--- Quote End ---  

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
83 Views

First problem I see: 

 

------------------------reset Memory------------------------ for i in 0 to 15 loop addr <= r_counter; r_counter := r_counter + 1; end loop;  

 

Your address actually increments by 16 on each clock, so the addresses in between are not written to. 

 

Also, you have included std_logic_unsigned and numeric_std. You should only use one or the other - (numeric_std is a standard package, std_logic_unsigned is not an IEEE standard). 

 

 

Did you have any problems other than these?
Reply