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Altera_Forum
Honored Contributor I
1,034 Views

what is the use of rClk[1..0]?

Hi all, 

 

What does the rClk[1..0] do in the system? the rClk[1] value is not used in the DE2_D5M demos but the register is added by 1 every clock cycle. The rClk[0] is then inverted from 0 to 1 every clock cycle, what is the use of this? 

 

Regards,
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4 Replies
Altera_Forum
Honored Contributor I
13 Views

A text search reveals, that rClk[0] is used in the design. rClk[1] isn't, simply ignore it, Quartus integrated synthesis will do, too.

Altera_Forum
Honored Contributor I
13 Views

Thanks, I see. But why does the design need to add 1 bit to the register? It just inverts the high signal to low.

Altera_Forum
Honored Contributor I
13 Views

Yes. The gate level logic is the same.  

 

As written, you have the option to generate a lower speed clock by connecting the output to rClk[1].
Altera_Forum
Honored Contributor I
13 Views

Okay, thank you very much :)