Order of code paths for SSE2 and AVX matters?

[Andrew_Smith]

In Intel Fortran 12 if I specify a default CPU architecture of AVX with an additional code path of SSE2 using /arch:AVX /QaxSSE2 I get illegal instruction errors runing on a machine without AVX. It does not appear to fall back to SSE2

But if I set it the other way around /arch:SSE2 /QaxAVX it runs OK on my SSE2 machine. I dont have an AVX machine to test but will it use AVX even though it is not the default?

Andy

[TimP]

According to my understanding, the "default" setting (which is preset to /arch:SSE2) should be the earliest architecture you wish to support. Your second quoted combination is OK, although you simply confirm the preset "default," in the opposite from usual order. The compiler will generate SSE2 code, and an additional AVX path when it determines there is sufficient added value.

[mecej4]

> I dont have an AVX machine to test but will it use AVX even though it is not the default?

You can, of course, read through the descriptions of the compiler options to find out what the compiler is expected to do, but you can find out if the produced .OBJ file has AVX instructions without needing to have a CPU with AVX capabilities. If you do not know the compiler switches used in producing, say, a library, this is one approach to answering the question.
On a laptop with a C2D (T4300), I compiled the Netlib ddot.f using the command

ifort /Fa /arch:SSE2 /QxAVX /c ddot.f

The assembly file produced contains, among others, the AVX instruction

vxorpd xmm0, xmm0, xmm0

If there is no alternative path that, based on the host CPU ID, enables bypassing this instruction, running an application obtained by linking this .OBJ file with others, on a C2D, will produce an illegal instruction trap.

Another approach is to let the Intel startup code detect the CPU and tell you if it cannot run the code.

[Steven_L_Intel1]

Tim's response is correct. What you did in the first combination was tell the compiler that AVX was the minimum instruction set.

[jimdempseyatthecove]

Then ought not the compiler issue a warning of meaningless (confusing) options?
i.e. when the OP optioned

minimum instruction support has AVX
alternate path if processor supports SSE2

One could interpret the above switch combination as resultingin SSE2 path always being taken (even on AVX system) due to AVX systems also supporting alternate SSE2 instruction set.

.OR. on the other hand

Ought not the compiler, under options given above, assume minimum instruction set is least capable and alternate set(s) are more capable. (and not issue warning).

Jim Dempsey

[Steven_L_Intel1]

Thanks for the suggestion, Jim.