Intel® Fortran Compiler
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Use on non-Intel processors (aka AMD processors)

lewist57
Novice
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Simple question: it is logical to assume that any code produced by the Intel Fortran compiler will be optimized for Intel processors (as per their web site), but is it safe to assume that the executable will work on non-Intel processors, just not optimized?

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Ron_Green
Moderator
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It will run on non-Intel processors.  There will be optimizations and good vectorization.  

Look up the -xHOST option https://www.intel.com/content/www/us/en/develop/documentation/fortran-compiler-oneapi-dev-guide-and-reference/top/compiler-reference/compiler-options/code-generation-options/xhost-qxhost.html#xhost-qxhost

 

and look for the AVX2 targeting.  Most processors from the last 6 years or more should have AVX2.  

xHOST is a good option to use for you.

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Bart_O_
Novice
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Note though there seems to be a bug in Intel Classic compilers >= 19.1 where it falls back to x87 instructions (not even SSE2, I think it's the equivalent of -march=pentium, the original one from 1993) on AMD for -xHOST (for both C(++) and Fortran). -march=core-avx2 works fine, and the oneAPI compilers work fine too. see also here:

https://community.intel.com/t5/Intel-Fortran-Compiler/SSE-error-in-compilation-with-xHost-option-on-AMD-Zen-3-CPU/m-p/1287143

 

$ lscpu | grep Model\ name
Model name: AMD EPYC 7532 32-Core Processor

$ ifort -v
ifort version 2021.6.0

$ cat test-amd.f90
program testamd

DOUBLE PRECISION :: y

read *,y
print *,y**2

end program

$ ifort -c -xHOST test-amd.f90

$ objdump -d test-amd.o

...

59: dd 44 24 40 fldl 0x40(%rsp)
5d: 48 8d 3c 24 lea (%rsp),%rdi
61: d8 c8 fmul %st(0),%st
63: 4c 8d 44 24 50 lea 0x50(%rsp),%r8
68: be ff ff ff ff mov $0xffffffff,%esi
6d: 48 ba 00 ff 84 83 20 movabs $0x1208384ff00,%rdx
74: 01 00 00
77: b9 00 00 00 00 mov $0x0,%ecx
7c: 33 c0 xor %eax,%eax
7e: 48 c7 07 00 00 00 00 movq $0x0,(%rdi)
85: dd 5f 50 fstpl 0x50(%rdi)

...

$ ifort -c -march=core-avx2 test-amd.f90

$ objdump -d test-amd.o

...

6a: c5 fb 10 44 24 40 vmovsd 0x40(%rsp),%xmm0
70: 48 8d 3c 24 lea (%rsp),%rdi
74: c5 fb 59 c8 vmulsd %xmm0,%xmm0,%xmm1
78: 4c 8d 44 24 50 lea 0x50(%rsp),%r8
7d: be ff ff ff ff mov $0xffffffff,%esi
82: 48 ba 00 ff 84 83 20 movabs $0x1208384ff00,%rdx
89: 01 00 00
8c: b9 00 00 00 00 mov $0x0,%ecx
91: 33 c0 xor %eax,%eax
93: 48 c7 07 00 00 00 00 movq $0x0,(%rdi)
9a: c5 fb 11 4f 50 vmovsd %xmm1,0x50(%rdi)

...

 

 

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