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I am trying to compile a simple CL kernel for my FPGA Cyclone V PCI-E Card.
No matter what I do, the compiler always returns an error after the synthesis is completed.
Error (11720): Run Analysis and Synthesis (quartus_map) with top-level entity name "top" before running Fitter (quartus_fit)
looking a the log I see that quartus_map command was issues to start the process, I don't understand what the problem is.
Thanks to all who can assist!
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Hi @B_Developer,
Thank you for posting in Intel community forum, hope this message find you well and apologies for the delayed in response.
Suspecting that the top level files might not be specified, after specifying, fit the top files to see if that works, please do refer to the steps in this session here for further details.
Best Wishes
BB
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Hi @B_Developer,
Greetings, unfortunately as we do not receive any further clarification on what is provided. Hence this thread will now be transitioned to community support. If you have new queries or further query on this thread, please feel free to open a new thread or reopen this thread to get support from us. Otherwise, the community users will further help you with doubts in this thread.
Best Wishes
BB
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