Basic/conceptual questions for DPC++FPGA example

[dj-park]

Hi, I am familiar with Xilinx Vitis and am trying to migrate to Intel oneAPI. The tutorials have been really helpful so far. (https://github.com/oneapi-src/oneAPI-samples)

I have a couple basic and conceptual questions.

1. In GettingStarted/fast_recompile example, 

I ran the command below to generate "dev_image.a".

icpx -fsycl -fintelfpga -fsycl-link=image kernel.cpp -o dev_image.a -Xshardware -Xstarget=agilex -I ../../../../include/

I checked the generated Quartus project, but it didn't run the quartus_asm which generates bitstream(.sof file).  How does the final "fast_recompile.fpga" configure the FPGA then?

2. Can I independently generate a Quartus project, generate a output like "dev_image.a" and integrate with the final device link with the command below?

icpx -fsycl -fintelfpga host.o dev_image.a -o fast_recompile.fpga

I am not sure whether there exists a command  that  translates Quartus's output(as far as I know, it's .sof file) to "dev_image.a" file so that the icpx command above can integrate the device image with the host code. Especially, I want to use Partial Reconfiguration with oneAPI (e.g. mapping multiple kernels to multiple PR regions).

Please correct me if my understanding is incorrect. Thanks in advance.

[BoonBengT_Altera]

Hi @dj-park;

Thank you for posting in Intel community forum and hope all is well.

If I understand your first question correctly, I would say the "fast_recompile.fpga" bitstream is more toward to be executed in the FPGA instead of configuring them, on top of that .fpga bitstream requires BSP which this fpga design generated from the compiler will than be included into the BSP framework. (which are different purposes from the .sof bitstream which are generally contain data for configuring the SRAM based intel devices)

As for the second part of the question, unfortunately there is no such use case available, hence no such command in quartus are available. In quartus itself there would be a different build flow are being utilize to generate the bitsteam which will than be be used to configured and run in the FPGA.

Hope that clarify.

Best Wishes

BB

[dj-park]

Thanks for the reply.

... more toward to be executed in the FPGA instead of configuring them. ...

I am confused with the phrase above.
So, "fast_recompile.fpga" should definitely contain bitstream to program FPGA, right?
What do you mean by "executed", and how is it different from "configuring" FPGA?

For me, icpx command is a blackbox. I want to know exactly how .a image file is generated from Quartus, and what exactly happens with the command below.

icpx -fsycl -fintelfpga host.o dev_image.a -o fast_recompile.fpga

[BoonBengT_Altera]

Hi @dj-park,

There are some explain that is being provided to explain the param/flag that is purposes for the icpx command as below:

https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/GettingStarted/fpga_compile

As for the question on .a image in relation to quartus question, allow me to get back to you after some alignment internally.

Thank you for the patients

Best Wishes

BB

[dj-park]

Ok, thanks! Please let me know the update.

[BoonBengT_Altera]

Hi @dj-park,

Thank you for the patients, after some alignment, understood that the a. image and other image files generated from quartus are different type of naming convension for bitstream and also to differentiate those bitstream on the technology used. Hope that explains.

Also a. device image are currently used on the oneAPI not the Quartus, hence generating it from Quartus would be not possible for now. Mind if I ask is there any use case that you are looking at for this?

Hope to hear from you soon.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dj-park,

Greetings, just checking in to see if there is any further doubts in regards to this matter.

Hope we have clarify your doubts.

Best Wishes

BB

[dj-park]

So, I want to have more flexibility while using oneAPI.
For instance, one use case could be Partial Reconfiguration with oneAPI.
Based on what you said, it seems impossible with the current oneAPI/Quartus.

[BoonBengT_Altera]

Hi @dj-park,

Unfortunately, per my understanding as of current it is not possible with oneapi features, however you would be able to tap along with the fpga addon with quartus to utilize this features .

Noted and thanks for sharing the use case mention, we would definitely take that into the consideration with the product team. 

Thank you for the patients.

Best Wishes

BB

[BoonBengT_Altera]

Hi @dj-park,

Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB