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Hi,
I am having some quartus fitter issues when compiling my OpenCL kernel on Intel DevCloud Stratix 10 (The command line "aoc -v -report -profile -O3 -fp-relaxed backprojection3D_kernel.cl -o bin/backprojection3D_kernel.aocx -board="pac_s10_dc" was used). The compiler outpout below:
!===========================================================================
! The report below may be inaccurate. A more comprehensive
! resource usage report can be found at backprojection3D_kernel/reports/report.html
!===========================================================================
+--------------------------------------------------------------------+
; Estimated Resource Usage Summary ;
+----------------------------------------+---------------------------+
; Resource + Usage ;
+----------------------------------------+---------------------------+
; Logic utilization ; 74% ;
; ALUTs ; 48% ;
; Dedicated logic registers ; 31% ;
; Memory blocks ; 64% ;
; DSP blocks ; 14% ;
+----------------------------------------+---------------------------;
aoc: First stage compilation completed successfully.
Compiling for FPGA. This process may take a long time, please be patient.
Error (170143): Final fitting attempt was unsuccessful
Error: An error occurred during routing
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 818 warnings
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 4016 warnings
Error (23035): Tcl error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Error (23031): Evaluation of Tcl script s10_partial_reconfig/flow.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 9 errors, 4016 warnings
Error (16546): Cannot load final database - ensure all earlier stages of the compiler have completed.
Error (17941): The design could not be loaded due to errors.
Error (23035): Tcl error:
Error (23031): Evaluation of Tcl script scripts/adjust_plls_mcp.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 4 errors, 0 warnings
Wed May 27 11:51:53 PDT 2020
!===========================================================================
I think it's due to the high logic utilization but I'm not sure if Stratix 10 has this issue.
Any help would appreciate.
Thank you !
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Hi,
Can you attached your kernal files to see if we can duplicate it?
The error message show: Error: An error occurred during routing
seems like the design was unable to route, might due to congestion issue. Can you try to reduce some code in your kernel?
Thanks
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Hi,
I changed my kernel code a bit, the kernel contains four nested loops, and I had many versions for optimizations purpose. It worked when I changed the combination of the loops unrolling factors. The two innermost loops of the kernel version, which does not route, had an unrolling factor of 8 each.
Thank you!
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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