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I am doing an image processing project based on FPGA. The first work I need to do is flipping the image horizontally. I think there is no problems in my program (the program is attached). There are also the screenshots of Platform Designer design and Programmer design. I think these are OK but after uploading the program into FPGA which is connected with the display screen, it suggests the uploading is successful but nothing displayed on the screen. I am not sure where I make mistakes. Maybe because I forget some important steps? Could anyone help me check where the problem is? Thanks a lot.
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Hi,
Looking at the details you provided, issue could by lying around any block video IP, image data flipping using HLS..
Did you verified the HLS module in standalone setup by simulation to see if it is performing as you expected ?
You can write testbench in C to verify that or setup a standalone simulation of generated component.
Thanks,
Arslan
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