I'm learning how to optimize C++ code for efficient high-level synthesis.
I'm looking at the memory banking code provided in Quartus Prime Pro hls/examples/tutorials folder.
One piece of code is shown like below:
According to what I understand, this should generate single memory bank with two store ports and two load ports. However, when opening the synthesis report, memory view shows as below:
First I can understand the initialization store can reuse the same store ports with the other two stores.
What I don't understand is why the other two stores share the same store port.
And when I click the share symbol, it says at the bottom, accesses are mutually exclusive, no arbitration? How can the two stores be mutually exclusive?
Thank you for posting in Intel community forum and hope this message find you well.
The behavior you are noticing should be part of the HLS merging memories trying to reduce area required.
Please do refer to the following details explanation here and hope it helps you to understand better.
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