Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
607 Discussions

HLS Main Optimizer FAILED. How can I debug it?



command :

i++ -v  -march=5CSEBA6U23I7 --debug-log --simulator none --quartus-compile -o test-fpga


HLS Main Optimizer FAILED.

make: *** [test-fpga] Error 1

It’s just that the feedback failed in the end, but it didn’t give me any other tips. How can I debug it?


Other information:

  • OS version: Redhat 6
  • HLS Compiler version: 18.1
  • Logfile: Only provide the command

Thanks in Advance!


0 Kudos
5 Replies
New Contributor I

can u attach debug.log generated after running the command??

if u want to compile quartus project, u can use quartus gui software to open and synthesize ur generated proj. From the GUI, it can provide more information.


Thanks for your advice.

There is only one line of command in debug.log, and then there is no other information.

I only know using Quartus HLS compiler to do high level synthesis. How to use Quartus GUI to do HLS?

I use Quartus Prime Lite 18.1 to connect IP and design system, but I don't know it can synthesis IP.

Are there any related tutorials or guide documents?


New Contributor I

I am also trying hls but 19.1 version since 2wk ago. at first, i tried with linux but thing did not go well. so im running it on window now. It can run smoother. after having right experience, i ll move back to linux later.  i suggest u to try a non-lite version on a virtual machine, get 30 day trial license to get it through, go through intel hls examples first, read the manual carefully. 

Here something u can try now.
- check if hls support CycloneV or not
- try hls with Arria10 (all hls versions support arria10)
- run the following command



# --debug-log -v -ghdl --> turn on all logging feature
i++ -v  -march=Arria10 --debug-log -v -ghdl --simulator none -o test-fpga
# should see a new folder test-fpga.proj. inside it, there are subfolders: components, quartus, reports, verification
# synthesize component with quartus
i++ -v  -march=Arria10 --debug-log -v -ghdl --quartus-compile
# or u can use quartus to open project <ur project folder>\test-fpga.proj\quartus\quartus_compile.qsf




Valued Contributor III

The crash here is happening in the C to RTL conversion step and hence, there is not RTL project to put into Quartus. The optimizer FAILED error typically happens when your design is too complex or not FPGA-friendly, and the compiler fails to generate RTL from it. There is generally no way of debugging this issue. The only remedy is to start small and compile your code step by step and add more components to it as you go to see when the crash happens, or redo your design completely and write it in a more FPGA-friendly manner.


Hi ,

If you cannot share the code , you can provide a pseudo code with giving the HLS specific calls and number of iterations of loops etc.

If you have Iterations you can try reducing the number and see the results. Also

Please make sure that you follow the instructions related to Quartus requirements while targeting Cyclone® V with HLS compiler.

1.3. Installing the Intel HLS Compiler Pro Edition for Cyclone® V Device Support

Thanks and Regards