How do the descriptors get stored in the local sram of the Intel DSA (Data Streaming Accelerators)?

[UnitedWebSoft]

My question is about Intel DSA (Data Streaming Accelerator). Intel DSA, according to the docs, can handle up to 256 queues and 65536 items (the bit width of registers are 8 and 16 respectively). Do you write the hardware to the DDR, or do you just keep all the descriptors in the sram on your machine?

[hareesh]

Hi,

with this information not able to finalize the issue. we need some more information about board details, document details and which platform are you working?

please share this information.

[hareesh]

Hi,

any update?

[hareesh]

Hi,

pls go through bellow artical

https://www.intel.com/content/www/us/en/content-details/671116/intel-data-streaming-accelerator-architecture-specification.html?wapkw=Data%20Streaming%20Accelerator

[hareesh]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.