How to compile 534 simplified lines?

[VFerr9]

Hello, everybody.

I'm using Altera Quartus 13, 64 bits for web.

I was studying Computation Theory, NonDeterministic Stack Automata, and I had some trouble with code simplification.

When my code is not simplified, it compiles. (At some point in spacetime I've gotten aula8.sof)

When I try to simplify, removing old_ variables, it does not compile. It stays forever at 2% compilation.

Maybe I'm totally wrong... Maybe some compilation directive... Maybe some new feature...

Please, forward it to he who makes quartus next release.

Thanks,

Vinicius Claudino Ferraz, from Brazil

@mathspiritual

[Vicky1]

Hi,

I tried to compile both the codes provided by you but your working code is also not compiling completely, it got stuck at 42% & not working code got stuck at 11% for Quartus 18.1 Lite quartus tool so according to your code few loops may not allowing/ending to compiler to compile the code successfully. please follow recommended HDL coding style,

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51007.pdf

Regards,

Vicky

[VFerr9]

Vicky, sometimes I had to wait 45 minutes of compilation, like that 1970's show.

i'm going to see your coding style, next year.

so you did not like my loops. but you don't doubt it compiled. do you?

this file is the start of the struggle. first I tested, it did not compile. I went down to older revision to compile.

in that file I made little changes and it compiled somehow.

then I've got the *.sof (I did not have time to install it in any FPGL to see the behaviour.)

the day after, I tested again, but it did not compile again.

So compilation is not deterministic. It is a stochastic process. 50% chances for compiling the same code today or tomorrow.

[Vicky1]

Hi,

Please provide your latest working project file(*qar)('Project' Menu->'Archive Project') for replication.

Regards,

Vicky

[VFerr9]

OK, attachments to this question have been updated. Go on and download replicated, archived and projected file.

Persistently,

facebook.com/mathspirituality

[Vicky1]

Hi Vinicius,

We can not see your attachment in Intel community, please attach Project file(*.qar) using 'Attach File' option at the bottom left end of the post window.

Regards,

Vicky

[VFerr9]

No. Nothing wrong. There are already 6 attachments. Check out the 5th one.

[Vicky1]

Hi Vinicius,

"Hi,

Please provide your latest working project file(*qar)('Project' Menu->'Archive Project') for replication.

Regards,

Vicky" ---------- I request you again please provide working *qar Archive file for replication as an attachment.

Regards,

Vicky

[VFerr9]

No. Nothing wrong. There are already 6 attachments.

Sexual problem detected.

Ask your boss: << do you see six attachments? Because Vinicius sees six attachments since December Eleventh. >>

[Vicky1]

Hi Vinicius,

Sexual problem detected. -------- In Intel FPGA community we support only FPGA development & devices related issues so rest of things you need to take care.

Ask your boss: << do you see six attachments? Because Vinicius sees six attachments since December Eleventh. >> ------- Sure.

I'm using Altera Quartus 13, 64 bits for web.

Please, forward it to he who makes quartus next release. ----------- Have you verified with latest Quartus version? please provide specific error/issue.

https://fpgasoftware.intel.com/18.1/?edition=lite&platform=windows

People in Intel community are not here to simplify or analyze your projects, they will help you to narrow down your issues if you cooperate them.

Now I would like to suggest,

1. Try to compile first your design without error In Quartus latest version & provide screenshot & if you face any error, let us know.
2. Once it compile successfully then verify it by writing the testbench & tracing waveform.
3. Then take backup of it & try to simplify with proper HDL syntax & language constraints.
4. If you need any online training please go through the below link,

https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

Regards,

Vicky

[VFerr9]

Hello, Vicky.

I did not like discussion about 6 attachments. Your QAR is there. Don't doubt. From zero:

I studied VHDL with Web release given from my professor.

I tested at home.

I went to school. I used FPGL with success.

Again, I changed at home. Tested with success.

I could not go to school. (End of semester.) I don't know if that *.sof is what I wanted.

Simply, I reported everything to the professor and I've sent copy of full story to the people who made the compiler.

The story is: your compiler compiles sometimes, other times it does not compile deterministically.

There is an incremental compilation, but...

Everybody wants a compiler which does the same thing today and tomorrow.

I know how to solve this with 1 processor. (Java, Delphi, Kylix, C++).

Without 1 processor, I only know FPGA and the old protoboards.

The goal was to report those news. If "the company" knows there was a problem with release 13 for Web (free release)

and if "the company" has as its 2020's priorities to fix it,

then there is nothing else to discuss.