I've seen that Intel FPGA SDK supports I/O channels (for example network channel) in a very basic way: the programmer can send/receive raw data (of a given size according the board specification) and these channels behave exactly like normal channels.
My questions are: there is a way to support a network stack with this I/O channels? I have seen that Intel offer Ethernet IP cores (for Quartus): are they amenable to be integrated with OpenCL?
Thanks for your help,
Some board manufacturers (e.g. Nallatech) provide a specific BSP for network communication that [I think] supports quick UDP protocol. However, you will need to purchase the Intel low-latency MAC core to be able to use that which is pretty expensive. You can indeed also modify the BSP yourself and add whatever protocol/interface you want on top of the existing interface.
Yes, but you don't need to build the BSP from scratch. If your board already has a BSP, you can modify that, and if it doesn't, you can use the BSPs from Intel's reference boards as basis.
Hi @TDe M1 ,
You can process UDP packets using the Nallatech (now BittWare) MAC BSP available on some FPGA boards like the Arria 10 385A for example.
Please review the content on the "Board Support Packages" tab at this address for further information:
This solution is ready to use. You would not need to write any HDL. I would recommend you contact BittWare's sales team for information about pricing.
Then definitely tool come with Ethernet IP . you can instantiate the IP and use it.
Can you let me know if you have further question on related topic?
Thank you ,