Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Novice
148 Views

I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Error message running bin/host from the command line:

Error: Unable to find function name clGetProfileInfoIntelFPGA in board library /glob/development-tools/versions/oneapi/beta05/inteloneapi/compiler/2021.1-beta05/linux/lib/oclfpga/board/intel_a10gx_pac/linux64/lib/libintel_opae_mmd.so (0x564ce15e96a0)

 

FYI there are a couple of warnings when I run "aocl diagnose -icd-only' on an fpga_runtime node, although the diagnositc claims that it passes:

 

 For /etc/OpenCL/vendors/Altera.icd, "WARNING: /glob/development-tools/versions/oneapi/beta04/inteloneapi/compiler/2021.1-beta04/linux/lib/oclfpga/host/linux64/lib/libalteracl.so NOT FOUND"

 

 For /etc/OpenCL/vendors/intel-neo.icd, "WARNING: libigdrcl.so NOT FOUND"

 

0 Kudos
11 Replies
Highlighted
Novice
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

The solution was to compile the host code on an fpga_compile node rather than on the fpga_runtime node.

 

I had the opposite problem with fast emulation, where it was necessary to compile the code on the fpga_runtime node for the program to be able to find the emulation platform at run time (on either type of node).

 

It would be nice to be able to compile host code for emulation or profiling on either type of node.

Highlighted
Employee
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Hi,

I am checking the information internally with developer.

By using 'devcloud_login', you could be able to choose the login node with device. May I know which login node you are trying to login to node s001-n138 for Intel PAC A10 device?

Thanks

0 Kudos
Highlighted
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Hi,

You need to reference the setup described here:

https://github.com/intel/FPGA-Devcloud/tree/master/main/QuickStartGuides/OneAPI_Program_PAC_Quicksta...

 

There are other Quickstart guides and useful information here: https://github.com/intel/FPGA-Devcloud

 

Note that it is important that you run the OneAPI commands on specific machines that have Ubuntu 18 loaded. You can find out the OS release with the command cat /etc/os-release . The Quickstart guide describes how to use the devcloud_login command to login interactively on a compute node that supports OneAPI and then run the tools_setup command to access the oneAPI.

 

Let us know if that works out okay for you.

 

Kind Regards

Larry

 

 

0 Kudos
Highlighted
Novice
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Sorry, I should have mentioned that I was using the OpenCL development flow when encountering the problems I described above, not OneAPI. As I said, I found a workaround for those issues which required compiling the host code on an fpga_compile node (s001-145 to s001-156) for profiling on a pac_a10 board, but required compiling the host code on an fpga_runtime node (s001-081 to s001-102) for emulation.

 

When I did use the OneAPI flow to build the vector-add example as in "https://devcloud.intel.com/oneapi/get-started/base-toolkit/#get-started-with-the-intel-oneapi-base-t...", the instructions said to build the design on an fpga_compile node and to run it on a pac_a10 board in an fpga_runtime node, and I tried followed that pattern when building and and profiling a design using the OpenCL development flow, which is how I encountered the problem I originally described.

 

However, as the quickstart guide example you referred to does both the build and the run on an fpga_runtime node, is it safe to assume that's a reasonable thing to do, etiquette-wise, or should designs generally be built on fpga_compile nodes, at least if they are likely to take long time?

 

I did successfully build and run that quickstart example. Is there a way to do profiling using OneAPI?

 

Thanks,

Dennis

0 Kudos
Highlighted
Employee
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Hi, 

 

Based on my understanding, it should be able to do profiling using OneAPI with tool called VTune. 

For more information about this tool, you may need to refer to the link as below: 

1. https://github.com/intel/BaseKit-code-samples/tree/master/Training/06_Intel_VTune_Profiler

2. https://software.intel.com/content/www/us/en/develop/documentation/vtune-help/top/command-line-inter...

 

Thanks

 

0 Kudos
Highlighted
Novice
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Thanks for the links, that was very helpful.

Using that information, I was able to compile the OneAPI vector-add example with profiling enabled (by adding the "-Xsprofile" option to the command line).

I then tried to obtain the profiling information by running the command "vtune -collect=fpga-interaction vector-add.fpga" on an fpga-runtime node, but got the following error messages:

 

vtune: Warning: Access to /proc/kallsyms file is limited. Consider changing /proc/sys/kernel/kptr_restrict to 0 to enable resolution of OS kernel and kernel module symbols.

vtune: Warning: To profile kernel modules during the session, make sure they are available in the /lib/modules/kernel_version/ location.

vtune: Error: Binary `vector-add.fpga' cannot be executed. Suggestion: Make sure the file exists, specified location is correct, and you have privileges to run the file.

vtune: Collection failed.

 

I'm not really sure what that means, given that that the vector-add.fpga executable was in the directory in which I ran the command.

I had no trouble running the executable without using vtune, but of course could not obtain the profiling information.

Is there something else I need to do?

 

0 Kudos
Highlighted
Employee
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Hi,

 

Based on the warning and error, provided you might need to the file you profiling is available in the location /lib/modules/kernel_version/ location.

Also, you may need to make sure all the file is able to read and write by using command "chmod 777".

 If there is any new error found, you may need to file a new forum case to better support.

Thanks

0 Kudos
Highlighted
Novice
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

While the directory " /lib/modules/kernel_version/ " exists, it has no subdirectory "kernel_version",

and since these directories are only writeable by root on the devcloud fpga_runtime node, I couldn't

change them if I wanted to.

 

The error message seems to imply that I am trying to profile the Linux kernel, which I have no interest in doing.

I'm only trying to profile the OneAPI FPGA application.

 

0 Kudos
Highlighted
Employee
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

Hi,

According to the link: https://github.com/intel/BaseKit-code-samples/tree/master/VtuneProfiler/matrix_multiply_vtune, the .dpcpp file is compiled. Could you try on this?

Thanks

0 Kudos
Highlighted
Novice
38 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a clGetProfileInfoIntelFPGA() call, but when I run it I get the error listed in the Details.

I did pull that example, and I can run it using vtune on a gen9 node of devcloud.

It also warns about accessing the /proc/kallsyms file, so apparently that is normal.

 

I still have the problem that when I try to run my vector-add executable with vtune on a devcloud fpga_run node I get an error, but when I run it without vtune it works fine. Is there an example somewhere of how to used vtune with an FPGA board?

 

0 Kudos
Highlighted
Employee
5 Views

Re: I can build a pac_a10 design for profiling on devcloud, and compile the host code containing a c

Hi, 

It seems like it could not be accessed to used in FPGA and there only example to use vtune to fpga via command line  in link: https://software.intel.com/content/www/us/en/develop/documentation/vtune-help/top/command-line-inter...

If more question for vtune on fpga support, you may need to post a new forum for better support on this.

Thanks

0 Kudos