I need to clarify a question about verilog

[BlackByte10xy]

Hello everybody,

I'm studying the primitives in verilog and I don't really see any use for them. I explain:

Imagine you want to describe an AND gate, what would you do?

a) assign OUT = A & B;

b) and (OUT, A, B);

So what is the true power of primitives? Why do they exist?

I have seen that users can create our own primitives (UDP), but the reasoning I have is the same: Why use this option of the verilog if we can describe our circuit with a "module"?

Thanks

[Nurina]

Hi,

Primitives take up lower memory and can improve simulation performance. Based on my understanding this is because the primitives' behaviour are specified using look-up tables. This method can be helpful because some elements in an FPGA project can be conveniently defined by just using a truth table(combinational) or state table(sequential).

Nurina

[Nurina]

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

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