I'm studying the primitives in verilog and I don't really see any use for them. I explain:
Imagine you want to describe an AND gate, what would you do?
a) assign OUT = A & B;
b) and (OUT, A, B);
So what is the true power of primitives? Why do they exist?
I have seen that users can create our own primitives (UDP), but the reasoning I have is the same: Why use this option of the verilog if we can describe our circuit with a "module"?
Primitives take up lower memory and can improve simulation performance. Based on my understanding this is because the primitives' behaviour are specified using look-up tables. This method can be helpful because some elements in an FPGA project can be conveniently defined by just using a truth table(combinational) or state table(sequential).
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