Interfacing DDR3 with DSP Builder. Adressbus size?

[TKlei]

Hi,

I'm using DSP Builder with External Memory Write block to store data in an DDR3 RAM. However the generated memory address size ist 27 bit and not 22 as expected with the memory size configuration. In the dsp builder model the size is correct (see attached Image).

In the generated design file the Memory address bus is defined as:

Memory_Write_address : out std_logic_vector(26 downto 0); -- ufix27

After looking into the source files I discovered this:

-- Memory_Write_gnd_x(CONSTANT,5) Memory_Write_gnd_x_q <= "00000"; -- Memory_Write_address_join_x(BITJOIN,2)@4 Memory_Write_address_join_x_q <= Memory_Write_address_reg_x_q & Memory_Write_gnd_x_q;

Why is the address joined with "00000"?

[NurAida_A_Intel]

Hi Sir,

Good day to you.

May I know if you configure any 27 bits in your design (maybe at high level) ? And do you observed any functional/simulation failure with this generated memory address size of 22 bits?

Thanks

Regards,

NAli1

[TKlei]

​Hi NAli1,

There is no 27 bit in this design. Please find attached the design.

Regards

Thomas

[NurAida_A_Intel]

​Hi Sir,

Please accept my apology for the delay in response.

Are you having Avalon MM interface 256 bits, if yes, then it is make sense to have “00000”.

My understand is that, if your Avalon MM interface is 64 bits, you will read out 64 bits per cycle, so the byte address is (64/8= 8 or 1000), so it has to padded/joined with 3 zero (bit 0-2 are not used). For your case, I believe, the Avalon MM interface is 256 bits, 256/8 = 32 (10 0000), so they will see it is padded with “00000”.  So, if you having Avalon MM interface 256 bits, then it make sense to have "00000".

Hope this helps.

Thanks

Regards,

NAli1