Modular approach for the NIOS ii processor intigration with main FPGA file

[Noman3]

I am currently working on integrating the Nios II processor with the main VHDL file in Quartus Prime. So far, I’ve successfully implemented PWM signal generation by assigning a constant angle using the Nios II processor.

My next goal is to make this system modular, so it can support N angles instead of just one. In my previous implementation, I used a single PIO (Parallel I/O) and assigned a base address to it.

Now, I’d like to know:

• Is it possible to automatically assign addresses for multiple angles (i.e., for multiple PIOs corresponding to each angle)?

• If so, what’s the best approach to manage or generate these addresses dynamically in a modular way?

I’ve also attached the files from my previous implementation for reference.

[JingyangTeh_Altera · Accepted solution]

Hi

One method is you could just add in multiple PIO IP and lock the addresses.

This can be done by clicking the little lock icon.

The Addresses of the PIO IP will be fix if you add in additional IPs to the project, this will not mess up the base address of the PIO IPs.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Do you have any follow up question on this?

Regards

Jingyang, Teh

[Noman3]

Many thanks Jingyang of your suport. I have done it by considring the alternating approach.

Regards 
Noman

[JingyangTeh_Altera]

Hi

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh