PR on agilex and how to use multi channel dma p tile for pcie?

[lcl]

We have a task to implement PR function，we have find some projects on github，below

https://github.com/intel/fpga-partial-reconfig/tree/master/ref_designs

but my fpga is agilex AGFB023R25A2E3V，I need to change the model of the fpga from s10 to agilex，in this process，pcie IP from s10  to agilex(multi channel dma p tile for pcie),finally we  get the .sof file。

After we program the FPGA, access the bar space through mem,it is timeout, and there is no write or read signal on the sinaltap is pulled high.

Can you provide a demo with PR on agilex？

also when we only use multi channel dma p tile for pcie (agilex PCIE IP ),access the bar space through mem,it also is timeout.

thank you，Looking forward to your reply！

[wchiah]

Hi ,

For Partial Reconfig (Agilex) you may refer to AN 953

https://www.intel.com/content/www/us/en/docs/programmable/683849/21-1/partially-reconfiguring-a-design-on.html#:~:text=The%20partial%20reconfiguration%20(PR)%20feature,in%20areas%20outside%20this%20region.

If you need to bring up the system, you may get our golden board design and .sof file from

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/f-series/dev-agf014.html

Hope this helpful.

Regards,

Wei Chuan

[lcl]

hi，

we know AN 953，but we need download bitstream from PICE ，now we access the bar space through wcdma that is busy，so what should we do？

thank you，Looking forward to your reply！

[wchiah]

Hi,

What do you mean bar space through wcdma that is busy ?
can you describe more on that? is there any error message show up ?

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[wchiah]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

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