aoc: Quartus is not on the path! - Devcloud

[RJimé1]

Hello,

I have suddenly come across the error aoc: Quartus is not on the path! on DevCloud when I was trying to compile a kernel with aoc. I was doing so from a node that is supposed to have Quartus, since I requested so with

qsub -I -l nodes=1:fpga_compile:ppn=2 -d .

This has been working since I started using DevCloud (the last time I used it successfully was last week). What is going on?

I managed to solve the issue by sourcing the script /data/intel_fpga/devcloudLoginToolSetup.sh and calling the function tools_setup afterwards. I found the solution here https://forums.intel.com/s/question/0D50P00004bTqr9SAC/devcloud-unable-to-compile-for-fpgas-aoc-quartus-is-not-on-the-path?language=en_US. However, this only removes the error aoc: Quartus is not on the path!, but a new error has arised:

Error: Internal Compiler Error. BSP specified project name dcp, but dcp.qpf does not exist.

I really need this working, since I am in a deadline.

Thank you.

[JSchr20]

Helo,

I am encountering this same problem. Thanks for your solution above; I am trying it and things are at least running. How long did it take for this new error to show up (how far into the quartus build)?

I agree, none of this used to be necessary. I assume this is the result of them switching over to 20.1. I don't know if it's possible to point back at 19.4, but if you can, that might work better. Maybe. :-)

Thank you!

[RJimé1]

Hi,

The error comes up as soon as aoc hits this stage:

aoc: Compiling for FPGA. This process may take several hours to complete. Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets. If the reports indicate performance targets are not being met, code edits may be required. Please refer to the Intel FPGA SDK for OpenCL Best Practices Guide for information on performance tuning applications for FPGAs.

This happens in a minute or so... Haven't you seen it? I'm using the 19.3 version of the compiler, by the way. The function I pointed out allows to choose the Quartus version you want.

Thank you.

[JSchr20]

Oh, that's a shame that changing aoc versions doesn't help.

BTW, is your design a OneAPI design (SYCL) or an OpenCL design at heart? Mine's entirely OpenCL.

Both my builds failed last night in identical ways. I left them running after I watched them get up to at least 10 minutes wall clock time, so when I looked this morning and saw your note that your builds had failed within a minute or so, I was hopeful. However, it was not to be. I submitted these as batch jobs, so I get an error and output file. The error file says this:

WARNING: this job is dumping too much data into the standard error stream. This log is truncated.

=>> PBS: job killed: walltime 21602 exceeded limit 21600

The output file says this:

########################################################################

#     Date:          Wed May 6 16:05:42 PDT 2020

#   Job ID:          591614.v-qsvr-1.aidevcloud

#     User:          u40073

# Resources:          neednodes=1:fpga_compile:ppn=2,nodes=1:fpga_compile:ppn=2,walltime=06:00:00

########################################################################

WARNING: this job is dumping too much data into the standard output stream. This log is truncated.

########################################################################

# End of output for job 591614.v-qsvr-1.aidevcloud

# Date: Wed May 6 22:05:48 PDT 2020

########################################################################

That is the sum total of the output I got from either job. I checked the bin directories to which I'd directed the output, hoping there'd be compilation directories in there with logs I could look at (this supposed excessive error data), but both directories were empty.

They apparently take their log truncation pretty seriously. :-)

Please let me know if you find any solution to your compilation woes. I'll do the same.

Thank you!

[RJimé1]

Mine is a pure OpenCL design as well.

I'll post here the solution if a find any, but it seems unlikely... I hope someone from Intel can come up with a fix.

Thank you.

[JSchr20]

Things have gone from bad to worse today in the dev cloud (see https://forums.intel.com/s/question/0D50P00004fMGpxSAG/oneapi-dev-clouds-a-hot-mess-today), but I have one additional data point regarding our particular problem here:

I tried to do a hardware build of the OpenCL vector_add example. I had built this example about a month ago on the dev cloud using 19.3 or whatever version was the default at that time. It built and ran fine on the a10_pac card. Today, I set off the build (using the environment setup you suggested above) and the build ran for all six allotted hours (it normally completes in under an hour) and then exited with the exact same error and output messages I reported above. Again, the bin target directory was empty.

[MEIYAN_L_Intel]

Hi,

May I know do you have setup for connecting to servers running FPGA development software as described in chapter 5:

https://github.com/intel/FPGA-Devcloud/tree/master/main/QuickStartGuides/OneAPI_Program_PAC_Quickstart/Arria%2010

There is OpenCL Quickstart guides in Devcloud and useful information here: 

https://github.com/intel/FPGA-Devcloud/tree/master/main/QuickStartGuides/OpenCL_Program_PAC_Quickstart/Arria%2010

Thanks

[RJimé1]

I can follow the steps described in the first link you provided successfully, but that doesn't enable me to compile for OpenCL. It seems the solution for that is in the second link. However, when I launch the devcloud_login function, choose the first option and later either one of the two new available options, I get this error:

running: qsub -q batch@v-qsvr-fpga -I -l nodes=s005-n004:ppn=2

qsub: submit error (Unauthorized Request MSG=group ACL is not satisfied: user u39146@login-2, queue batch)

It seems I lack some permissions. Besides, none of this was necessary a week ago, I could simply request a node with compiling capabilities by specifying the property fpga_compile to qsub.

Thank you.

[JSchr20]

Like RJimé1, I am working with a purely OpenCL design.

I, also, followed the instructions at the second link, and I encountered the same qsub submit error mentioned by RJimé1 above.

I agree as well that none of this environmental hoop jumping was necessary a week ago. We were set up properly to do this stuff automatically at login.

[JSchr20]

I think I have something that's working. First, the devcloud environment has clearly improved this afternoon, so I'm unsure whether this would have worked yesterday. But no matter, I have tentative hope that is working today. I believe I can now build FPGA hardware again.

Interactive mode:

qsub -I -l nodes=1:fpga_compile:ppn=2

source /data/intel_fpga/devcloudLoginToolSetup.sh

aoc device/vector_add.cl -o bin/vector_add_hw.aocx

Batch mode:

file build_fpga_hw.sh contains:

#!/bin/bash

source /data/intel_fpga/devcloudLoginToolSetup.sh

aoc device/vector_add.cl -o bin/vector_add_hw.aocx

Then, from login-2, I run:

qsub -l nodes=1:fpga_compile:ppn=2 -d . -o logs -e logs build_fpga_hw.sh

I am not positive this will complete successfully, but it has been running for 15 minutes and hasn't died yet, which is a hopeful sign.

Turns out what I was doing wrong yesterday with my six hour builds was that I had the line "tools_setup" in my batch shell file after the setup script, because that's what the instructions indicated. I didn't realize that was an interactive command, so my batch jobs spent six hours waiting on keyboard input. Oops. Seems one needs to run the setup script (without that, we still get the "dcp.qpf does not exist" error), but one should *not* run tools_setup or devcloud_login.

[RJimé1]

This has already been fixed. I can compile kernels as I did one week before. There's no need to use any script.

Thank you @JSchr20​  for your implication.

[JSchr20]

RJimé1, that's great to hear. That definitely wasn't the case last Friday. Intel has clearly improved the environment. I appreciate your assistance!

[MEIYAN_L_Intel]

Hi,

Thanks for information and update.

Thanks

[RJimé1]

Hello again,

As I stated in my last post, I am now capable of compiling kernels with AOC 20.1 and everything works like a charm. However, I still need to use the old version (19.3) of the compiler because my solution was designed around it. I thought it would be as simple as using the aoc binary located at /glob/development-tools/versions/intelFPGA_pro/19.3/hld/bin/, but, although the compilation completes successfully I get the error CL_INVALID_BINARY (-42) in OpenCL. Can you help me with that?

[MEIYAN_L_Intel]

Hi,

According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_getting_started.pdf in chapter 1.1.1 stated that you can use older version BSP in newer Intel OpenCL compiler. It is not possible to use newer BSP with older Intel OpenCL compiler.

Thanks

[RJimé1]

Ok, thank you. It seems I have to make my design work with the new version of the compiler.

[MEIYAN_L_Intel]

Hi,

Thanks for information and update.

Thanks