Intel® High Level Design
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meeting failure when I compile code for D5005

jimbook
Beginner
734 Views
$dpcpp -fintelfpga -Xshardware -Xstarget=intel_s10sx_pac:pac_s10 fpga_compile.cpp -o main.fpga aoc: Compiling for FPGA. This process may take several hours to complete. Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets. If the reports indicate performance targets are not being met, code edits may be required. Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs. For more details, full Quartus compile output can be found in files quartuserr.tmp and quartus_sh_compile.log. Error: Compiler Error, not able to generate hardware llvm-foreach: dpcpp: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
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hareesh
Employee
686 Views

Hi,

Can you please give more information about your issue. what type of issues are you facing and share your error screen shots.


Thanks,


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hareesh
Employee
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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