I've posted a discussion on this topic before, but I don't know why I can't reply to the comment of the employee of Intel, so I posted this post again
What I want to say is: I can successfully download JIC files through quartus programmer, but what I want is to capture the success signal of whether DDR is initialized successfully through signal tap. Downloading sof files through programmer can not help me see the success signal. I can only download sof files through signal tap
My original request for help was:When I use the IP core of HPS and the IP core of DDR4 to build a project, I want to use the signal tap to see whether DDR4 is initialized successfully. However, when I download the generated sof file to the FPGA board on the signal tap interface, the system reports an error: the sof file is incomplete - HPS is present but the boot loader is missing
