Guaranteed atomic operation clarification

[Nathan_P_]

Hello,

I'm trying to understand a line in the Intel Architecture manual. It's a description of a memory operation that is guaranteed to be atomic.

The line is at Chapter 8, Section 8.1.1 "Guaranteed Atomic Operations", second bullet list, second item:
>16-bit accesses to uncached memory locations that fit within a 32-bit data bus

The way I interpret this (which must be wrong) is: Accesses to 16-bit regions of memory that are not currently cached and that fit within a data bus that transfers 32-bit values.

I assume this is wrong, because a 16-bit region would always fit on a 32-bit bus.

Does anyone know what this line is meant to say?

[McCalpinJohn · Accepted solution]

The unstated assumption is that the data bus always transfers naturally aligned 32-bit values, while the 16-bit value may or may not be naturally aligned.   If the 16-bit value starts on an odd byte position, half of the time the data would fit in one 32-bit naturally aligned bus transfer, and half of the time the 16-bit value would straddle two 32-bit naturally aligned bus transfers.

E.g., The bus transfers bytes 0-3, 4-7, 8-11, etc., while the requests are for bytes 1-2 (ok), 3-4 (bad), 5-6 (ok), 7-8 (bad), etc.

[Nathan_P_]

I see what you mean! Makes sense. Thanks very much.