My question is about Intel Core 2 Duo processor when local APIC is disabled and NMI and INTR pins are connected to an external PIC(programmable interrupt controller). Interrupt comes but how interrupt is acknowledged by CPU on FSB (front side bus)? I mean what signals and pins of the processor will eventually generate an interupt acknowledge cycle (on PCI bus)?
Why data sheet of Core 2 Duo does not explain such a scenario?
