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Got the message that for CPU shifting from AVX/AVX512 power lane to SSE power lane, if there is no 'vzeroupper' instruction invoked, a very long (tens of cycles) penalty will generated. With my simple test code, I found the AVX512 to SSE transition could not be captured by SDE9.7.0, but it could be recognized by emon. Please have an investigation.
Huaqiang
Thanks.
My test code:
// ---- test code -----
int main(){
std::cout << "AVX-SSE Penalty" << std::endl;
asm("vzeroupper");
// AVX512 -> SSE -> AVX512
asm("vbroadcastsd (%rbp), %zmm0");
asm("movq %rax, %xmm8");
asm("vbroadcastsd (%rbp), %zmm0");
asm("vzeroupper");
return 0;
}
---- EMON Test Result: ----
2 ASSISTS.SSE_AVX_MIX event captured
ASSISTS.SSE_AVX_MIX also reports the event for AVX512-SSE transition.
(base) [root@host avx-sse]# emon -C "ASSISTS.SSE_AVX_MIX" /bin/taskset -c 1 ./ast-penalty
AVX-SSE Penalty
Version Info: V11.34 (May 1 2022 at 22:02:55) Intel(R) Xeon(R) Processor code named Sapphirerapids M:143 S:3
ASSISTS.SSE_AVX_MIX 5,700,234,584 0 2 0 0 0 0 0 0 0 0 0
---- Sde64 result ----
[No AVX-SSE transition found]
(base) [root@host avx-sse]# sde64 -ast -- ./ast-penalty
AVX-SSE Penalty
(base) [root@host avx-sse]# tail -n 10 sde-avx-sse-transition-out.txt
Block Transition Transition Icount Executions Icount Block Block
================ ============ ============ ======== ========== ======== ================ ================
# SUMMARY
# AVX_to_SSE_transition_instances: 0
# SSE_to_AVX_transition_instances: 0
# Dynamic_insts: 2803115
# AVX_to_SSE_instances/instruction: 0.0000
# SSE_to_AVX_instances/instruction: 0.0000
# AVX_to_SSE_instances/100instructions: 0.0000
# SSE_to_AVX_instances/100instructions: 0.0000
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The AVX-SSE transition checker was developed at the Intel AVX time frame (before AVX-512) and was never updated to support also Intel AVX-512 instructions. We will check the option of adding this support.
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SDE and the Pintool are a great tools, very like to use it. Thanks your team for bringing them out! Hope to have new feature also!
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